Size can be 16KB-2MB.

Fixed line length of 32 bytes, eight words.

300 MHz worst case with 0.18 micron technology operating frequency range.

Physically addressed and physically tagged.

Lockdown format C supported, with separate way locking mechanisms for data and instructions.

Eight-way associativity which can be direct mapped, depending on the use of lockdown registers.

Data RAM is byte-writable.

Support for these cache modes:

Write allocate override option to always have allocation on write misses in the cache controller.

Performs critical word first refilling, with the option of refilling starting with word 0. The same option is used to transform nonbufferable wrap write bursts and noncacheable wrap read bursts into linear accesses.

Pseudo-random victim selection policy, can be made deterministic with use of lockdown registers.

You can statically configure the following options:

Static option to select synchronous or asynchronous master port interfaces

Parity generation and error detection synthesis option.