2.7. Ports configuration

To simplify AMBA ports design, some of their characteristics have to be configured using the following pins:

Those characteristics are:

Number of master ports, if present after synthesis

The cache controller can work with three, two, M0 and M1, or one, M1 only, master ports. The choice is made by forcing the correct value on MASTNUM[1:0] input pins.

MASTNUM[1:0] is a static input. If its value is changed while the cache controller is in use, even if it is disabled, the result is Unpredictable.

Number of slave ports, if present after synthesis

The cache controller can work with three, two, S0 and S1, or one, S1 only, slave ports. The choice is made by forcing the correct value on the SLAVENUM[1:0] input pins.

SLAVENUM[1:0] is a static input. If its value is changed while the cache controller is in use, even if it is disabled, the result is Unpredictable.

Data bus sizes

32-bit wide or 64-bit wide data buses can be configured on a per-port basis. Six input pins, SIZES0, SIZES1, SIZES2, SIZEM0, SIZEM1, and SIZEM2 can be forced to configure all three slave and three master ports independently. These are static inputs. If their values are changed while the cache controller is in use, even if it is disabled, the result is Unpredictable.

Endianness

The cache controller must be aware of the endianness of the system in which it sits. The cache controller BIGEND input pin must be tied to the correct value.

BIGEND is a static input. If its value is changed while the cache controller is in use, even if it is disabled, the result is Unpredictable.

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