1.3.5. Configuring the cache controller

The cache controller is configured using memory-mapped registers. See Chapter 2 Programmer’s Model for details.

The cache controller is highly configurable. You do not have to resynthesize the module to reconfigure the cache controller for other applications. This means that you only have to harden the cache controller macrocell once, regardless of the number of cache controller configurations you use.You can use synthesis options to remove S0,S2, M0, and M2. If S0 is not implemented, then M0 must also be removed. S0,S2, M0, and M2, if present, can be disabled using the MASTNUM and SLAVENUM pins. This means that you can harden a cache controller with all ports and disable unused ones in a specific SoC. S1 always exists in all configurations.

Port configurations

This section describes the different configurations of slave ports and master ports:

Slave ports

There are three requesting ports to the cache controller, the AHB slave ports:

S0 AHB Slave port 0

Only services reads.

S1 AHB Slave port 1

Services both reads and writes, and services swaps. It is the only port that can read the internal cache controller registers. All configurations must support this port

S2 AHB Slave port 2

Only services writes.

All slave ports support exclusive accesses and locked accesses.

For more information see Locked accesses and Exclusive accesses.

The cache controller can work with three, two, S0 and S1, or one, S1 only, slave ports. You choose the number of slave ports by forcing the correct value on the SLAVENUM[1:0] input pins. Clocks of unused slaves are inactive in functional mode (static high-level clock gating).

Master ports

Table 1.2, Table 1.3, and Table 1.4 show which transactions each master port is used for in the three possible master port configurations.

The cache controller can work with three, two, M0 and M1, or one, M1 only, master ports. You choose the number of slave ports by forcing the correct value on the MASTNUM[1:0] input pins. Clocks of unused slaves are inactive in functional mode (static high-level clock gating).

Table 1-2 shows the transactions on the three master ports in a three-master system. For certain types of transactions the default values for HMASTERM1 and HMASTERM2 are configurable in the cache controller RTL, see Appendix A Signal Descriptions.

Note

In Appendix A Signal Descriptions, the default values for HMASTERM1 and HMASTERM2 on certain types of transactions are configured as 0xF.

Table 1.2. Transactions for a three-master port system

Master port 0Master port 1Master port 2
Linefills with linefill buffer 0Linefills with linefill buffer 1Buffered stores with eviction buffer
Noncached readsNoncached readsBuffered stores with write buffer
-Swaps, noncached reads andnonbufferable writesNonbuffered stores

Table 1.3 shows the transactions on the two master ports in a two-master system.

Table 1.3. Transactions for a two-master port system

Master port 0Master port 1
Linefills with linefill buffer 0Linefills with linefill buffer 1
Noncached readsNoncached reads
-Swaps, noncached reads andnonbufferable writes
Buffered stores with eviction buffer
Buffered stores with write buffer
Nonbuffered stores

Table 1.4 shows the transactions on the single master port, master port 1, in a single-master port system.

Table 1.4. Transactions for a single-master port system

Master port 1
Linefills with linefill buffer 1 only
All noncached reads
Swaps, noncached reads, andnonbufferable writes
Buffered stores with eviction buffer
Buffered stores with write buffer
Nonbuffered stores
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