D.1. ARM1136 memory system configurations

Figure D.1 shows an ARM 1136 memory system using all three slave ports and the signals output on a three-master configuration, a two-master configuration and a single-master configuration.

Figure D.1. ARM1136 memory system with cache controller master port configurations

See Behavior for ARMv6 memory systems for information on ARMv6 memory system cache transactions.

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