6.1. Parity and RAM error support

The cache controller generates parity write data for the data and tag RAMs as shown in Figure 6.1. For the data RAM, the cache controller generates parity write data on a per-byte basis. For the tag RAMs, the cache controller generates one parity bit that must be routed to all tag RAMs. Only one tag RAM is written at any one time so only one bit is required. The generation and checking of parity data is disabled if bit 21 of the Auxiliary Control Register is set to 0 as described in Auxiliary Control Register.

For AHB read transactions, if a parity error occurs on tag or data RAM, an error is reported back to HRESPSx and through the event bus.

For AHB write transactions and cache maintenance operations, if a parity error occurs on tag or data RAM, tag RAM only for AHB write transactions, the error is reported back through the event bus only.

Figure 6.1. Parity and RAM error support

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