L210 Cache Controller Technical Reference ManualRevision r0p5
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2.3.1. ID Register

The read-only ID Register returns a 32-bit device ID code. The device id is specified by the value tied on the CACHEID[5:0] input.

You can access the ID Register by reading from the cache controller base address + 0x000. Figure 2.1 shows the format of the ID Register.

Figure 2.1. ID Register

Table 2.3 shows the encoding of the ID Register.

Table 2.3. ID Register encoding

Register bits

Function

Values

[31:24]

RTL implementor

0x41

[23:16]Read as zero (RAZ)

-

[15:10]Input pins for layout implementor-
[9:6]Part number index0x1
[5:0]RTL release indexSee Table 2.4

Table 2.4 shows the release number index values

Table 2.4. Release number index values and releases

Release number indexRelease
0x0Fr0p5
0x0Br0p4
0x03r0p3
0x02r0p2_01
0x01r0p1
0x00r0p2_02
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