C.2. Programmer’s model

The cache controller event monitor is accessed through a set of memory-mapped registers that occupy a relocatable 4KB region of memory. The base address of the cache controller is not fixed, but is determined by an AHB decoder on the slave buses and can be different for any particular system implementation. However, the offset of any particular register from the base address is fixed.

The registers are accessed through an AHB-Lite slave interface. The cache controller event monitor contains ten registers. Table C.1 shows this.

Table C.1. Event monitor registers

Register Function Address
EMMC Event Monitor Control BASE + 0x000
EMCS Counter status register BASE + 0x004
EMCC0 Counter 0 configuration BASE + 0x100
EMCC1 Counter 1 configuration BASE + 0x104
EMCC2 Counter 2 configuration BASE + 0x108
EMCC3 Counter 3 configuration BASE + 0x10C
EMC0 (read-only) Counter 0 BASE + 0x200
EMC1 (read-only) Counter 1 BASE + 0x204
EMC2 (read-only) Counter 2 BASE + 0x208
EMC3 (read-only) Counter 3 BASE + 0x20C
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