The cache controller is delivered with an event monitor block template that is intended to be plugged onto the cache controller event bus. It can be reshaped by the licensee to meet their system requirements.

The addition of an event monitor block in a system that contains an ARM processor and a cache controller enables monitoring of events and errors in the RAMs that make up the cache controller. This information can be used to tune the overall system performance.

To optimize the performance of a system, the cache controller event monitor block provides four event counters, EMN0-EMN3. They can be used to count the instances of four different events selected from a list of possible external events, through the cache controller event bus, or internal events such as overflows or clock edges. Each counter is a 32-bit counter and has its own interrupt generation logic. By combining different statistics, you can obtain a variety of performance metrics.

The example system described in this Appendix has the following features: