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The cache controller event monitor block appears as an AHB slave to the CPU. All transactions to the cache controller event monitor are seen as single 32-bit AHB transactions. HSIZE, HBURST, and HPROT pins are not required.
The slave always answers with HRESP = 00 (OKAY). This means that:
Non 32-bit transactions, HSIZE b010, is always treated as a 32-bit transaction.
A read to an unmapped register always returns b0000.
A write to an unmapped register is silently discarded.
| Copyright © 2003-2006 ARM Limited. All rights reserved. | ARM DDI 0284G |
| Non-Confidential | |
| PDF version | |
| Home > Event Monitor > Implementation details |