D.3.1. L2 off or noncacheable read accesses

This section describes two states:

Wrap access disabled, L2 off or noncacheable read accesses

To achieve wrap access disabled, the Auxiliary Control Register bit[12] is set to 1. When using 64-bit wide master ports, all INCRn burst transactions are kept unchanged. When using 32-bit wide master ports and the size of the burst is a doubleword, then the burst changes are as follows:

  • INCR4 => INCR8

  • INCR8 => INCR16

  • INCR16 => INCR

Table D.1 shows the WRAPn read access conversions on slave ports.

Table D.1. WRAPn read access conversions on slave ports

SizeMaster widthWRAP4WRAP8WRAP16
Byte-INCR4INCR82 x INCR
Halfword-INCR4INCR82 x INCR
Word-INCR4INCR82 x INCR
Doubleword64-bit wide master portINCR42 x INCR2 x INCR
 32-bit wide master portINCR82 x INCR2 x INCR

Wrap access enabled, L2 off or noncacheable read access

To achieve wrap access enabled, the Auxiliary Control Register bit[12] is set to 0. When using 32-bit wide master ports and the size of the burst is a doubleword, then the burst changes are as follows:

  • INCR4 => INCR8

  • INCR8 => INCR16

  • INCR16 => INCR

  • WRAP4 => WRAP8

  • WRAP8 => WRAP16

  • WRAP16 => 2 x INCR

Note

There are no changes for the other sizes.

Copyright © 2003-2006 ARM Limited. All rights reserved.ARM DDI 0284G
Non-Confidential