L210 Cache Controller Technical Reference Manual 3.2.1. Data RAM

Figure 3.1 shows the data RAM bus address format.

Figure 3.1. Data RAM bus address format

Bits [15:13] connections depend on cache associativity. Table 3.1 shows this.

Table 3.1. Cache associativity and bits[15:13] of data RAM bus address

Associativity	Connections
One or two way	Bits [15:14] are left unconnected. Bit 13 is the Most Significant Bit (MSB) of the RAM address bus.
Three or four way	Bit 15 is left unconnected. Bits [14:13] are MSBs of RAM address bus.
Five to eight way	Bits [15:13] are MSBs of RAM address bus.

Associativity

Connections

One or two way

Bits [15:14] are left unconnected.

Bit 13 is the Most Significant Bit (MSB) of the RAM address bus.

Three or four way

Bit 15 is left unconnected.

Bits [14:13] are MSBs of RAM address bus.

Five to eight way

Bits [15:13] are MSBs of RAM address bus.

Bits [12:0] connections depend on way size. Table 3.2 shows this.

Table 3.2. Way size and bits[12:0] of data RAM bus address

Way size	Connections
16KB	Bits [12:9] are left unconnected. Bits [8:0] are the Least Significant Bits (LSBs) of RAM address bus.
32KB	Bits [12:10] are left unconnected. Bits [9:0] are LSBs of RAM address bus.
64KB	Bits [12:11] are left unconnected. Bits [10:0] are LSBs of RAM address bus.
128KB	Bit 12 is left unconnected. Bits [11:0] are LSBs of RAM address bus.
256KB	Bits [12:0] are LSBs of RAM address bus.

All bits of the data bus are always connected.

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