4.7.2. Behavior for ARMv6 transactions

Table 4.6 shows memory types and the cache controller behavior for reads and writes.

Table 4.6. Behavior with ARMv6 memory types

Memory typeReadsWrites
Strongly Ordered (SO), Always Shared

Not cached in the L2.

Causes AHB master port access.

Not buffered.

Causes AHB master port access.

Device (DV), Always Shared

Not cached in the L2.

Causes AHB master port access.

Not buffered.

Causes AHB master port access.

Outer noncacheable (ONC), Nonshared, (Same as SO)

Not cached in the L2.

Causes AHB master port access.

Not buffered.

Causes AHB master port access.

Outer noncacheable (ONC), Shared, (Same as SO)

Not cached in the L2.

Causes AHB master port access.

Not buffered.

Causes AHB master port access.

Outer Write-Back write-allocate (OWBWA), nonshared

Read hit: Read from the L2.

Read miss: Linefill to the L2.

Write hit

Put in write buffer, write to the L2 when write buffer drained, and mark line as dirty.

Write miss

Put in write buffer, put in write-allocate buffer when write buffer drained, data request to L3 if line is not full, allocation to L2.

Outer Write-Back write-allocate (OWBWA), Shared

Not cached in the L2.

Causes AHB master port access.

Put in write buffer. Write to L3 when write buffer drained.

Outer Write-Through no-write-allocate (OWTNWA), nonshared

Read hit: Read from the L2.

Read miss: Linefill to the L2.

Write hit

Put in write buffer, write to L2, causes AHB master port access when write buffer drained.

Write miss

Put in write buffer, causes AHB master port access when write buffer drained.

Outer Write-Through no-write-allocate (OWTNWA), Shared

Not cached in the L2

Causes AHB master port access.

Put in write buffer, causes AHB master port access when write buffer drained.

Outer Write-Back no-write-allocate (OWBNWA), nonshared

Read hit: Read from the L2.

Read miss: Linefill to the L2.

Write hit: Put in write buffer, write to the cache controller when write buffer drained, mark line as dirty.

Write miss: put in write buffer, causes AHB master port access when write buffer drained.

Outer Write-Back no-write-allocate (OWBNWA), Shared

Not cached in the L2

Causes AHB master port access.

Put in write buffer, causes AHB master port access when write buffer drained.

Note

  • ARMv6 specifies that accesses from a processor to memory marked as Device must occur at the size and the order defined by the instruction. So, Device write accesses are treated by cache controller as nonbufferable because the write buffer is a merging write buffer.

  • Write allocate override causes all nonshared cacheable write misses, unless shared attribute override is set, to be allocated to the cache controller. Setting the shared attribute override bit in the Auxiliary Control Register causes a Shared access to be internally treated as NonShared in the cache controller. See Auxiliary Control Register for more information on the write allocate override bit and the shared attribute override bit.

  • No unexpected hits can occur on noncacheable accesses. Slave ports request a transfer to the internal cache controller or to the master port depending on access attributes. This means that no lookups are performed for noncacheable accesses.

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