1.1. About the Cache Controller

The addition of an on-chip secondary cache (also referred to as a Level 2 cache, L2CC) is a recognized method of improving the performance of computer systems when significant memory traffic is generated by the Central Processing Unit (CPU). By definition a secondary cache assumes the presence of a Level 1 or primary cache, closely coupled or internal to the CPU.

Memory access is fastest to L1 cache, followed closely by the L2 cache controller. Memory access is significantly slower with L3 memory, main memory. Table 1.1 shows typical sizes and access times for different types of memory.

Table 1.1. Typical memory sizes and access times

Memory typeSizeAccess time
Processor registers128 Bytes1 cycle
On-chip L1 cache32KB1-2 cycles
On-chip L210 Cache Controller128KB8 cycles
Main memory (L3) dynamic RAM

MB

GB [1]

16 cycles
Back-up memory (hard disk) (L4)

MB

GB

>500 cycles

[1] Size limited by the processor core addressing. For example, a 32-bit core without memory management can directly address 4GB of memory.

Copyright © 2003-2006 ARM Limited. All rights reserved.ARM DDI 0284G
Non-Confidential