L210 Cache Controller Technical Reference Manual 4.7.1. ARMv6 system transactions

L210 Cache Controller Technical Reference Manual

Revision r0p5

Home > Using the Cache Controller > Behavior for ARMv6 memory systems > ARMv6 system transactions

4.7.1. ARMv6 system transactions

In the case of a 32-bit interface, read data and write data on masters are treated as follows:

write data is on HWDATA[31:0], and HWDATA[63:32] is always 0.
read data must be duplicated on HRDATA[63:32] and HRDATA[31:0].

Table 4.5 shows the HPROTSx[4-2] and TLB correspondences in ARMv6.

Table 4.5. HPROTSx[4-2] and TLB correspondences in ARMv6

HSIDEBAND[1] Shared	HPROT[4]Allocate	HPROT[3]cacheable	HPROT[2] Bufferable	ARMv6 ARM1136 AMBA extensions	ARMv5 equivalent
-	0	0	0	Strongly ordered, always Shared No buffered writes, no linefills.	NCNB
-	0	0	1	Device, always Shared No linefills.	NCB
0	0	1	0	Outer noncacheable, nonshared No buffered writes, no linefills.	-
1	0	1	0	Outer noncacheable, shared No buffered writes, no linefills.	-
0	0	1	1	Outer Write-Back write-allocate (OWBWA) – nonshared Buffered writes on misses, linefills on reads and writes.	-
1	0	1	1	Outer Write-Back write-allocate (OWBWA) – Shared Buffered writes on misses, no linefills	-
-	1	0	-	N/A	-
0	1	1	0	Outer Write-Through no-write-allocate (OWTNWA) – nonshared Buffered writes, linefills on reads but not writes.	WT
1	1	1	0	Outer Write-Through no-write-allocate (OWTNWA) – Shared Buffered writes, no linefills	-
0	1	1	1	Outer Write-Back no-write-allocate (OWBNWA) – nonshared Buffered writes on misses, linefills on reads but no writes	WB
1	1	1	1	Outer Write-Back no-write-allocate (OWBNWA) – Shared Buffered writes on misses, no linefills	-

Copyright © 2003-2006 ARM Limited. All rights reserved.	ARM DDI 0284G
Non-Confidential
PDF version

Home > Using the Cache Controller > Behavior for ARMv6 memory systems > ARMv6 system transactions