4.7.1. ARMv6 system transactions

In the case of a 32-bit interface, read data and write data on masters are treated as follows:

Table 4.5 shows the HPROTSx[4-2] and TLB correspondences in ARMv6.

Table 4.5. HPROTSx[4-2] and TLB correspondences in ARMv6

HSIDEBAND[1] SharedHPROT[4]AllocateHPROT[3]cacheableHPROT[2] BufferableARMv6 ARM1136 AMBA extensionsARMv5 equivalent
-000

Strongly ordered, always Shared

No buffered writes, no linefills.

NCNB
-001

Device, always Shared

No linefills.

NCB
0010

Outer noncacheable, nonshared

No buffered writes, no linefills.

-
1010

Outer noncacheable, shared

No buffered writes, no linefills.

-
0011

Outer Write-Back write-allocate (OWBWA) – nonshared

Buffered writes on misses, linefills on reads and writes.

-
1011

Outer Write-Back write-allocate (OWBWA) – Shared

Buffered writes on misses, no linefills

-
-10-N/A-
0110

Outer Write-Through no-write-allocate (OWTNWA) – nonshared

Buffered writes, linefills on reads but not writes.

WT
1110

Outer Write-Through no-write-allocate (OWTNWA) – Shared

Buffered writes, no linefills

-
0111

Outer Write-Back no-write-allocate (OWBNWA) – nonshared

Buffered writes on misses, linefills on reads but no writes

WB
1111

Outer Write-Back no-write-allocate (OWBNWA) – Shared

Buffered writes on misses, no linefills

-
Copyright © 2003-2006 ARM Limited. All rights reserved.ARM DDI 0284G
Non-Confidential