L210 Cache Controller Technical Reference Manual 1.2. Cache controller block diagram

1.2. Cache controller block diagram

Figure 1.1 shows the internal data paths of the cache controller. It can be used in a system with an ARM1136 core, ARM1026 core, or ARM926EJ-S core.

Figure 1.1. Cache controller internal data paths

To enable flexibility, you can configure the cache controller to use one, two, or three ports. The cache controller ports are:

64-bit AHB-Lite slave ports
- One slave, S1
- Two slaves, S0 and S1
- Three slaves, S0, S1, and S2.
The cache controller arbitrates internally among them.
64-bit AHB-Lite master ports:
- One master, M1
- Two masters, M0 and M1
- Three masters, M0, M1, and M2.

If you decide not to use S0, you cannot configure M0. S1 always exists in all configurations.

The cache controller master ports are AHB-Lite compatible. ARM Limited can supply an AHB wrapper that converts the AHB-Lite interface to a multi-master AHB interface and that does not introduce any pipeline delays.

Copyright © 2003-2006 ARM Limited. All rights reserved.	ARM DDI 0284G
Non-Confidential
PDF version