The cache controller resets assume the slowest compiled RAMs are being used. This means eight cache controller clock cycles are used for each access. In terms of reads, the read data is sampled eight clock edges after the edge on which the RAM sampled the read request. Using this nomenclature, the shortest latency is one. This is the first latency example in Figure 4.1. The latencies for each RAM are programmed in the Auxiliary Control Register as shown in Auxiliary Control Register. See also Miscellaneous signals for descriptions of related signals. This register must only be programmed when the cache controller is not enabled.