4.6.2. Behavior for ARMv5 transactions

Table 4.4 shows cache controller behavior for ARMv5 transactions.

Table 4.4. Behavior for ARMv5 transactions

ARMv5 memory regionBehavior
NCNB

Read

Not cached in the L2, causes AHB master port access.

Write

Not buffered, causes AHB master port access.

NCB

Read

Not cached in the L2, causes AHB master port access.

Write

Not buffered, causes AHB master port access.

Cached

WT mode

Read hit

Read from the L2.

Read miss

Linefill to the L2, then forwarded to L1.

Write hit

Put in write buffer, write to the L2 when write buffer drained and causes AHB master port access when write buffer drained.

Write miss

Put in write buffer, causes AHB master port access when write buffer drained.

Cached

WB mode

Read hit

Read from the L2.

Read miss

Linefill to the L2, then forwarded to L1.

Write hit

Put in write buffer, write to the L2 when write buffer drained, mark line as dirty.

Write miss

Put in write buffer, causes AHB master port access when write buffer drained.

Write allocate override causes all cacheable writes misses to be allocated to the cache controller. See Auxiliary Control Register for a description of the write allocate override bit.

The write buffer is drained when the two slots contain data, the least used line is drained first, or in the case of hazards the line causing the hazard is drained. Refer to Write buffer for details about the write buffer.

Unaligned burst accesses and known length bursts

Unaligned burst accesses are not supported. If a noncacheable known length burst is early terminated on a slave port, the behavior of the master port handling the transaction is unpredictable.

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