D.3.2. L2 off or nonbufferable write accesses

This section describes two states:

Wrap access disabled, L2 off or nonbufferable write accesses

To achieve wrap access disabled, the Auxiliary Control Register bit[12] is set to 1. When using 64-bit wide master ports, all INCRn burst transactions are kept unchanged. When using 32-bit wide master ports and the size of the burst is a doubleword, then the burst changes are as follows:

  • INCR4 => INCR8

  • INCR8 => INCR16

  • INCR16 => INCR

All WRAPn write accesses are converted in two INCR bursts on the master side.

Wrap access enabled, L2 off or nonbufferable write accesses

To achieve wrap access enabled, the Auxiliary Control Register bit[12] is set to 0. When using 32-bit wide master ports and the size of the burst is a doubleword, then the burst changes are as follows:

  • INCR4 => INCR8

  • INCR8 => INCR16

  • INCR16 => INCR

  • WRAP4 => WRAP8

  • WRAP8 => WRAP16

  • WRAP16 => 2 x INCR

Note

There are no changes for the other sizes.

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