A.1.1. Slave port 0 signals

Table A.1 shows the slave port 0 signals.This assumes SO is present after synthesis.

Table A.1. Slave port 0 signals

SignalsInput/ outputDescription
CLKENS0InputCLK enable for slave port 0
HADDRS0[31:0]InputAddress bus
HBSTRBS0[7:0]InputByte lane strobes
HBURSTS0[2:0]Input

Burst length:

000 Single

001 Incr

010 Wrap4

011 Incr4

100 Wrap 8

101 Incr 8

110 Wrap 16

111 Incr 16

HMASTLOCKS0InputLocked transfer request
HMASTERS0[3:0]InputMaster ID for requested access
HPROTS0[5:0]InputProtection information associated with transfer
HSIDEBANDS0[3:0]InputSignals L1 and sharable attributes
HSIZES0[2:0]Input

Size of the AHB transfer:

Bit [2] is ignored.

Bits[1:0]

00 8-bit

01 16-bit

10 32-bit

11 64-bit

HTRANSS0[1:0]Input

AHB transfer type:

00 IDLE

01 BUSY

10 NSEQ

11 SEQ

HUNALIGNS0InputUnaligned access signal
HRDATAS0[63:0]OutputRead data bus
HREADYS0OutputDriven LOW to extend transfer
HRESPS0[2:0]OutputAHB transfer response
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