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Table A.1 shows the slave port 0 signals.This assumes SO is present after synthesis.
Table A.1. Slave port 0 signals
| Signals | Input/ output | Description |
|---|---|---|
| CLKENS0 | Input | CLK enable for slave port 0 |
| HADDRS0[31:0] | Input | Address bus |
| HBSTRBS0[7:0] | Input | Byte lane strobes |
| HBURSTS0[2:0] | Input | Burst length: 000 Single 001 Incr 010 Wrap4 011 Incr4 100 Wrap 8 101 Incr 8 110 Wrap 16 111 Incr 16 |
| HMASTLOCKS0 | Input | Locked transfer request |
| HMASTERS0[3:0] | Input | Master ID for requested access |
| HPROTS0[5:0] | Input | Protection information associated with transfer |
| HSIDEBANDS0[3:0] | Input | Signals L1 and sharable attributes |
| HSIZES0[2:0] | Input | Size of the AHB transfer: Bit [2] is ignored. Bits[1:0] 00 8-bit 01 16-bit 10 32-bit 11 64-bit |
| HTRANSS0[1:0] | Input | AHB transfer type: 00 IDLE 01 BUSY 10 NSEQ 11 SEQ |
| HUNALIGNS0 | Input | Unaligned access signal |
| HRDATAS0[63:0] | Output | Read data bus |
| HREADYS0 | Output | Driven LOW to extend transfer |
| HRESPS0[2:0] | Output | AHB transfer response |
| Copyright © 2003-2006 ARM Limited. All rights reserved. | ARM DDI 0284G |
| Non-Confidential | |
| PDF version | |
| Home > Signal Descriptions > Cache controller signals > Slave port 0 signals |