A.1.12. Miscellaneous signals

Table A.12 shows miscellaneous signals.

Table A.12. Miscellaneous signals

Signal nameInput/ outputDescription
BIGENDInputCPU core endianness, BE-32
CACHEID[5:0]Input

Value read on CACHE ID Register 0 bits [15:10] Reserved for layout Implementor. See ID Register for details.

CLKInputMain CPU or Cache controller clock
HCLKInputMain memory clock, the same as CLK for synchronous mode
HSELSR2ENInput Enable writes to internal registers through S2 port
HSYNCEN[1]Input

Synchronous mode enable

0 = The cache controller is in asynchronous mode of operation

1 = The cache controller is in synchronous mode of operation

MASTNUM[1:0]Input

Number of master ports:

00: one master, M101: two masters, M0 and M1

1x: three masters, M0, M1, and M2

SLAVENUM[1:0]Input

Number of slave ports:

00: one slave, S101: two slaves, S0 and S11x: three slaves, S0, S1, and S2

nHRESETInputReset signal for HCLK clock domain logic, active LOW
nRESETInputReset signal for CLK clock domain logic, active LOW
SIZEM0Input

Data bus size:

0 = 32 bits

1 = 64 bits

SIZEM1Input

Data bus size:

0 = 32 bits

1 = 64 bits

SIZEM2Input

Data bus size:

0 = 32 bits

1 = 64 bits

SIZES0Input

Data bus size:

0 = 32 bits

1 = 64 bits

SIZES1Input

Data bus size:

0 = 32 bits

1 = 64 bits

SIZES2Input

Data bus size:

0 = 32 bits

1 = 64 bits

TESTENInput

Test mode enable

Used to enable clocks of unused slaves or masters for test

CLKOUTOutputOutput clock signal for RAMs
DIRTYLAT[2:0]OutputValue set in bits[11:9] of the Auxiliary Control Register[2]
IDLEOutputThe cache controller is idle
RDATALAT[2:0]OutputValue set in bits[2:0] of the Auxiliary Control Register[3]
TAGLAT[2:0]OutputValue set in bits[8:6] of the Auxiliary Control Register[4]
WDATALAT[2:0]OutputValue set in bits[5:3] of the Auxiliary Control Register[5]

[1] HSYNCEN does not exist if the asynchronous interface has been removed by synthesis.

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