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Table A.12 shows miscellaneous signals.
Table A.12. Miscellaneous signals
| Signal name | Input/ output | Description |
|---|---|---|
| BIGEND | Input | CPU core endianness, BE-32 |
| CACHEID[5:0] | Input | Value read on CACHE ID Register 0 bits [15:10] Reserved for layout Implementor. See ID Register for details. |
| CLK | Input | Main CPU or Cache controller clock |
| HCLK | Input | Main memory clock, the same as CLK for synchronous mode |
| HSELSR2EN | Input | Enable writes to internal registers through S2 port |
| HSYNCEN[1] | Input | Synchronous mode enable 0 = The cache controller is in asynchronous mode of operation 1 = The cache controller is in synchronous mode of operation |
| MASTNUM[1:0] | Input | Number of master ports: 00: one master, M101: two masters, M0 and M1 1x: three masters, M0, M1, and M2 |
| SLAVENUM[1:0] | Input | Number of slave ports: 00: one slave, S101: two slaves, S0 and S11x: three slaves, S0, S1, and S2 |
| nHRESET | Input | Reset signal for HCLK clock domain logic, active LOW |
| nRESET | Input | Reset signal for CLK clock domain logic, active LOW |
| SIZEM0 | Input | Data bus size: 0 = 32 bits 1 = 64 bits |
| SIZEM1 | Input | Data bus size: 0 = 32 bits 1 = 64 bits |
| SIZEM2 | Input | Data bus size: 0 = 32 bits 1 = 64 bits |
| SIZES0 | Input | Data bus size: 0 = 32 bits 1 = 64 bits |
| SIZES1 | Input | Data bus size: 0 = 32 bits 1 = 64 bits |
| SIZES2 | Input | Data bus size: 0 = 32 bits 1 = 64 bits |
| TESTEN | Input | Test mode enable Used to enable clocks of unused slaves or masters for test |
| CLKOUT | Output | Output clock signal for RAMs |
| DIRTYLAT[2:0] | Output | Value set in bits[11:9] of the Auxiliary Control Register[2] |
| IDLE | Output | The cache controller is idle |
| RDATALAT[2:0] | Output | Value set in bits[2:0] of the Auxiliary Control Register[3] |
| TAGLAT[2:0] | Output | Value set in bits[8:6] of the Auxiliary Control Register[4] |
| WDATALAT[2:0] | Output | Value set in bits[5:3] of the Auxiliary Control Register[5] |
[1] HSYNCEN does not exist if the asynchronous interface has been removed by synthesis. [2] Described in Auxiliary Control Register. [3] Described in Auxiliary Control Register. [4] Described in Auxiliary Control Register. [5] Described in Auxiliary Control Register. | ||
| Copyright © 2003-2006 ARM Limited. All rights reserved. | ARM DDI 0284G |
| Non-Confidential | |
| PDF version | |
| Home > Signal Descriptions > Cache controller signals > Miscellaneous signals |