A.1.10. Cache controller event bus

Table A.10 shows the cache controller event bus output signals.

Table A.10. Cache controller event bus output signals

Signal nameNotes
BWABTBuffered write abort or abort caused by write-allocate buffer read
COCache line or half line eviction
DRHIT Data read hit in the L2 cache controller[1]
DRREQData read look-up to the L2 cache controller. This can subsequently hit or missa.
DWHITData write buffer write hit in the L2 cache
DWREQData write buffer write look-up to the L2 cache with Write-Through attribute. This can subsequently hit or miss.
DWTREQData write buffer write look-up with Write-Through attribute
ERRRDError on L2 data RAM read
ERRRTError on L2 tag RAM read
ERRWDError on L2 data RAM write
ERRWTError on L2 tag RAM write
IRHITInstruction read hit in the L2 cache controllera
IRREQInstruction read look-up to the L2 cache. This can subsequently hit or miss.
PARRDParity error on L2 data RAM read
PARRTParity error on L2 tag RAM read
WAAllocation into the L2 cache caused by a write, with Write-Allocate attribute, miss

[1] When data read requests hit in the slave line read buffer, no events are generated through these pins.

Copyright © 2003-2006 ARM Limited. All rights reserved.ARM DDI 0284G
Non-Confidential