L210 Cache Controller Technical Reference ManualRevision r0p5
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A.1.4. Master port 1 signals

Table A.4 shows the master port 1 signals.

Table A.4. Master port 1 signals

SignalsInput/ outputDescription
HCLKENM1InputHCLK enable for Master port 1
HRDATAM1[63:0]InputRead data bus
HREADYM1InputReady signal
HRESPM1[2:0]InputAHB transfer response
HADDRM1[31:0]OutputAddress bus
HBSTRBM1[7:0]OutputByte lane strobes
HBURSTM1[2:0]Output

Burst length

000 Single

001 Incr

010 Wrap4

011 Incr4

100 Wrap 8

101 Incr 8

110 Wrap 16

111 Incr 16

HMASTLOCKM1OutputLocked transfer request
HMASTERM1[3:0]Output

Master ID for requested access

HMASTERM1 information is only valid for L2 noncacheable nonbufferable accesses and linefills (read miss). HMASTERM1 takes 0xF as its default value for buffered writes, line evictions, linefills caused by write misses and the write allocate region.

HPROTM1[5:0]Output

Protection information associated with a transfer.

HPROTM1 information is always valid except for line evictions and linefills caused by a write miss, write allocate region. HPROTM1 takes 0x0F as its default value in these cases.

HSIDEBANDM1[3:0]Output

Signals L1 and sharable attributes.

HSIDEBANDM1 information is always valid except for line evictions and linefills caused by write miss, the write allocate region. HSIDEBANDM1 takes 0xE as its default value in these cases.

HSIZEM1[2:0]Output

Size of the AHB transfer

Bit [2] is ignored.

Bits[1:0]

00 8-bit

01 16-bit

10 32-bit

11 64-bit

HTRANSM1[1:0]Output

AHB transfer type:

00 IDLE

01 BUSY

10 NSEQ

11 SEQ

HUNALIGNM1OutputUnaligned access signal
HWDATAM1[63:0]OutputWrite data bus
HWRITEM1OutputWrite signal
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