A.1.3. Slave port 1 signals

Table A.3 shows the slave port 1 signals.

Table A.3. Slave port 1 signals

SignalsInput/ outputDescription
CLKENS1InputCLK enable for slave port 1
HADDRS1[31:0]InputAddress bus
HBSTRBS1[7:0]InputByte lane strobes
HBURSTS1[2:0]Input

Burst length

000 Single

001 Incr

010 Wrap4

011 Incr4

100 Wrap 8

101 Incr 8

110 Wrap 16

111 Incr 16

HMASTERS1[3:0]InputMaster ID for requested access
HMASTLOCKS1InputLocked transfer request
HPROTS1[5:0]InputProtection information associated with transfer
HSELRS1InputChip select for accessing internal registers
HSIDEBANDS1[3:0]InputSignals L1 and sharable attributes
HSIZES1[2:0]Input

Size of the AHB transfer

Bit [2] is ignored.

Bits[1:0]

00 8-bit

01 16-bit

10 32-bit

11 64-bit

HTRANSS1[1:0]Input

AHB transfer type:

00 IDLE

01 BUSY

10 NSEQ

11 SEQ

HUNALIGNS1InputUnaligned access signal
HWDATAS1[63:0]InputWrite data bus
HWRITES1InputWrite signal
HRDATAS1[63:0]OutputRead data bus
HREADYS1OutputDriven LOW to extend transfer
HRESPS1[2:0]OutputAHB transfer response
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