A.1.6. Master port 2 signals

Table A.6 shows the master port 2 signals. This assumes M2 is present after synthesis

Table A.6. Master port 2 signals

SignalsInput/ outputDescription
HCLKENM2InputHCLK enable for Master port 2
HREADYM2InputReady signal
HRESPM2[2:0]InputAHB transfer response
HADDRM2[31:0]OutputAddress bus
HBSTRBM2[7:0]OutputByte lane strobes
HBURSTM2[2:0]Output

Burst length

000 Single

001 Incr

010 Wrap4

011 Incr4

100 Wrap 8

101 Incr 8

110 Wrap 16

111 Incr 16

HMASTLOCKM2OutputLocked transfer request
HMASTERM2[3:0]Output

Master ID for requested access

HMASTERM2 information is only valid for L2 noncacheable nonbufferable accesses and linefills (read miss). HMASTERM2 information is always valid except for buffered write and line evictions. In these two cases HMASTERM2 takes 0xF as its default value.

HPROTM2[5:0]Output

Protection information associated with a transfer. HPROTM2 information is always valid except for line evictions. HPROTM2 takes 0x0F as its default value in this case.

HSIDEBANDM2[3:0]Output

Signals L1 and sharable attributes. HSIDEBANDM2 information is always valid except for line evictions. HSIDEBANDM2 takes 0xE as its default value in this case.

HSIZEM2[2:0]Output

Size of the AHB transfer

Bit [2] is ignored.

Bits[1:0]

00 8-bit

01 16-bit

10 32-bit

11 64-bit

HTRANSM2[1:0]Output

AHB transfer type:

00 IDLE

01 BUSY

10 NSEQ

11 SEQ

HUNALIGNM2OutputUnaligned access signal
HWDATAM2[63:0]OutputWrite data bus
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