A.1.5. Slave port 2 signals

Table A.5 shows the slave port 2 signals. This assumes S2 is present after synthesis

Table A.5. Slave port 2 signals

SignalsInput/ outputDescription
CLKENS2InputCLK enable for Slave port 2
HADDRS2[31:0]InputAddress bus
HBSTRBS2[7:0]InputByte lane strobes
HBURSTS2[2:0]Input

Burst length

000 Single

001 Incr

010 Wrap4

011 Incr4

100 Wrap 8

101 Incr 8

110 Wrap 16

111 Incr 16

HMASTERS2[3:0]InputMaster ID for requested access
HMASTLOCKS2InputLocked transfer request
HPROTS2[5:0]InputProtection information associated with transfer
HSELRS2InputChip select for accessing internal registers
HSIDEBANDS2[3:0]InputSignals L1 and sharable attributes
HSIZES2[2:0]Input

Size of the AHB transfer

Bit [2] is ignored.

Bits[1:0]

00 8-bit

01 16-bit

10 32-bit

11 64-bit

HTRANSS2[1:0]Input

AHB transfer type:

00 IDLE

01 BUSY

10 NSEQ

11 SEQ

HUNALIGNS2InputUnaligned access signal
HWDATAS2[63:0]InputWrite data bus
HREADYS2OutputDriven LOW to extend transfer
HRESPS2[2:0]OutputAHB transfer response
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