L210 Cache Controller Technical Reference ManualRevision r0p5
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A.1.7. Data RAM interface signals

Table A.7 shows the cache controller data RAM interface signals.

Table A.7. Data RAM interface signals

SignalsInput/ outputDescription
DATAERRInputData RAM error
DATAPRD[31:0]InputData RAM parity read data
DATARD[255:0]InputData RAM read data
DATAADDR[15:0]OutputData RAM address
DATACSOutputData RAM chip select
DATAEN[31:0]OutputData RAM byte write enables
DATAnRWOutputCurrent access to data RAM is a write
DATAPEN[31:0]OutputData parity RAM byte write enables
DATAPnRWOutputCurrent access to data parity RAM is a write
DATAPWD[31:0]OutputData RAM parity write data
DATAWD[255:0]OutputData RAM write data
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