L210 Cache Controller Technical Reference Manual 3.3. Data RAM

3.3. Data RAM

The data RAM is organized as eight ways of 256-bit wide contiguous memories. It supports the following accesses:

8-word data reads
8-word data writes for linefills.
8-bit, 16-bit, 32-bit, and 64-bit data writes for non-sequential or sequential writes with byte lane controls

Figure 3.2 shows the data RAM signals.

Figure 3.2. Data RAM signals

In all the following diagrams N is used to show the sizes of the RAMs. Table 3.6 shows how N is calculated.

Table 3.6. Values for N in RAM size diagrams

Figure 3.3 shows the data RAM ways.

Figure 3.3. Data RAM ways

Copyright © 2003-2006 ARM Limited. All rights reserved.	ARM DDI 0284G
Non-Confidential
PDF version