3.4. Tag RAM

Each way of the cache controller has one tag RAM. The tag RAM is organized as 19-bit wide, maximum, down to 15-bit wide memory:

The tag RAM address bus is also the address bus for the dirty RAM. The tag RAMs support the following accesses:

Figure 3.4 shows the tag RAM signals,

Figure 3.4. Tag RAM signals

Figure 3.5 shows how the tag RAM is organized. There is one tag RAM for each way.

Figure 3.5. Tag RAM organization

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