C.2.2. Counter Status Register, EMCS

The Counter Status Register contains a set of flags that indicate if the corresponding counter flag set condition, as described in Table C.3, has occurred. It is used to determine which counter or counters cause an interrupt if interrupt generation is enabled.

If the interrupt is programmed to be level sensitive, the interrupt line remains active until all flags in the Counter Status Register are cleared. Table C.3 describes the Counter Status Register bits.

Table C.3. Counter Status Register

BitField Description
[31:4] ReservedShould be Zero (SBZ)/RAZ
[3]EMC3 Flag 0

0 = Counter Flag set condition has not occurred

1 = Counter Flag set condition has occurred

Counter Flags are cleared when written to 1

[2]EMC2 Flag 1
[1]EMC1 Flag
[0] EMC0 Flag
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