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For each counter, a configuration register exists so that user can define:
counter event source
counter Flag set condition, flag is in Counter Status Register
interrupt enable.
Table C.4 shows the Counter Configuration Registers.
Table C.4. Counter Configuration Register
| Bit | Field | Description |
|---|---|---|
| [31:4] | Reserved | SBZ/RAZ |
| [6:2] | Counter event source | Table C.5 gives the encodings. |
| [1] | Counter Flag set condition | 0 = Counter flag set on overflow, default 1 = Counter flag set on increment |
| [0] | Counter interrupt generation enable | 0 = No interruption generated by the counter, default 1= An interrupt is generated when counter flag set condition is met |
| Copyright © 2003-2006 ARM Limited. All rights reserved. | ARM DDI 0284G |
| Non-Confidential | |
| PDF version | |
| Home > Event Monitor > Programmer’s model > Counter Configuration Registers, EMCCx |