C.2.3. Counter Configuration Registers, EMCCx

For each counter, a configuration register exists so that user can define:

Table C.4 shows the Counter Configuration Registers.

Table C.4. Counter Configuration Register

BitField Description
[31:4] Reserved SBZ/RAZ
[6:2]Counter event sourceTable C.5 gives the encodings.
[1] Counter Flag set condition

0 = Counter flag set on overflow, default

1 = Counter flag set on increment

[0]Counter interrupt generation enable

0 = No interruption generated by the counter, default

1= An interrupt is generated when counter flag set condition is met

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