C.3.2. Interrupts

The user can configure the cache controller event monitor to control precisely how interrupts are generated. Interrupt generation set-up is made in four steps

  1. Interrupt signal set-up.

    The interrupt line (INT) can be configured to be level-sensitive, interrupt tied to active level until interrupt is cleared, or edge sensitive, one pulse to active level, lasting a programmable number of CLK cycles and the active level is also configurable. In that way, the cache controller event monitor can be directly connected to the CPU, level-sensitive active LOW interrupt, or to any kind of interrupt controller.

  2. Counter set-up.

    For each counter, an incrementing trigger is chosen between all possible events.

  3. Counter Flag set condition set-up.

    Counter flags can be set on two conditions, increment or overflow. CCNT Flag is only set on overflow.

  4. Interruption enable.

    Set counter flags do not generate an interrupt until their interrupt enable bit is set.

Priority is given to the event. If a flag set condition occurs at the same cycle as the related flag is cleared by the CPU, the flag remains set. In this way a level-sensitive interrupt remains active.

Edge-sensitive interrupts obey these rules:

Copyright © 2003-2006 ARM Limited. All rights reserved.ARM DDI 0284G
Non-Confidential