C.3.3. AHB clocking

The AHB interface has its own clock, HCLK, that enables the memory system to run at a different frequency to the CPU core, the cache controller, and the event monitor. With respect to CLK, HCLK can be either:

Synchronous

HCLK frequency is the same or a submultiple of CLK frequency and the skew between the two clocks is minimal. HSYNCEN =1 in this case.

Asynchronous

There is no phase or frequency relation between HCLK and CLK. Like the ARM1136 core and the cache controller, the event monitor contains optional synchronization logic, synthesis option with HSYNCEN input pin set to 0, that enables asynchronous behavior.

In addition to HCLK, HCLKEN input is used to reduce the transfer rate on AHB bus to a ratio of HCLK. Figure C.1 shows this. All signals on AHB bus are considered valid, and so can be sampled, on HCLK rising edge when HCLKEN is HIGH. No assumption is made on synchronicity between CLK and HCLK in that case.

Figure C.1. HCLKEN usage for a read

Synchronous interface

When HSYNCEN is set to HIGH, l2cc_em module is fully synchronous. CLK and HCLK should be connected together to the same clock.

The AHB slave interface always responds with one wait state.

Asynchronous interface

When HSYNCEN is set to LOW, l2cc_em module is operating in asynchronous mode. No phase relation is assumed between HCLK and CLK.

The AHB slave interface generates wait states, by asserting HREADY LOW, as long as needed to ensure that the request is seen by the register module and the acknowledge is forwarded back to the AHB interface.

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