1.2.1. Operating frequency
For AHB slaves the clock is CLK,
the same clock as for internal cache controller logic. For AHB masters
the clock is HCLK
The CPU AHB ports of the cache controller can operate at the
same frequency as the CPU core. This means that the CPU core clock
and CLK operate in a 1:1 ratio.
All AMBA signals are considered valid on a rising clock edge
with HREADY high and HCLKEN high.
Timing diagrams shows
examples of typical cache controller bus transactions.
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