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The following known L2 hazards are all handled internally by the cache controller:
Read when in WB.
Read when in EB.
Read from S0 or S1, when in LFB1 or LFB0. This scenario also describes two reads, both arriving at the same time on different ports, to the same address.
Read when in WA.
Write when in LR0 or LR1.
Write when in LFB0 or LFB1.
Write when in EB.
| Copyright © 2003-2006 ARM Limited. All rights reserved. | ARM DDI 0284G |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model > Hazards > L2 hazards handled internally |