5.2.4. MBIST testing of the cache controller tag RAMs
There is one tag RAM for each way of the cache controller.
The maximum number of tag RAMs the MBIST controller must test is
eight. Only one tag RAM is tested at a time. Table 5.4 shows the address
range of MBISTADDR used to test
a tag RAM, based on the cache controller size. The parity bit for
each TAG RAM present is tested along with the rest of the TAG array
and is mapped to MBISTDIN[19].
Table 5.4. MBISTADDR and MBISTDIN mapping for Tag RAMs
| Size | Number of tag RAM indexes | MBISTADDR to RAM mapping | MBISTDIN to RAM mapping |
|---|
| 128KB | 512 | TAGADDR[8:0] = MBISTADDR[10:2] | TAGWD[19:0] = MBISTDIN[18:0, 19] |
| 256KB | 1 024 | TAGADDR[9:0] = MBISTADDR[11:2] | TAGWD[18:0] = MBISTDIN[18:1, 19] |
| 512KB | 2 048 | TAGADDR[10:0] = MBISTADDR[12:2] | TAGWD[17:0] = MBISTDIN[18:2, 19] |
| 1MB | 4 096 | TAGADDR[11:0] = MBISTADDR[13:2] | TAGWD[16:0] = MBISTDIN[18:3, 19] |
| 2MB | 8 192 | TAGADDR[12:0] = MBISTADDR[14:2] | TAGWD[15:0] = MBISTDIN[18:4, 19] |
The data from the tag RAMs is always registered by the cache
controller. In addition, there is a register on the MBIST port of
the cache controller. The cache controller always adds two register
delays to the MBIST data read path for the tag RAMs. The latency
of the tag RAMs can be from one to eight clock cycles as described
in MBIST compiled RAM latencies.
Figure 5.4 shows
the MBIST paths for tag RAM testing. In Figure 5.4 MBISTCE[8:1] is for chip enables to
the tag RAMs. MBISTCE[8:1] corresponds
to TAGCS[7:0]. MBISTDCTL[10:3] is for reads from previous
MBIST transactions, which controls the read data for Tag RAMs 7-0
respectively. The MBISTDCTL bit
corresponding to the required RAM read data must be asserted on the
same cycle that the read data is available at the output of the
RAM, and all other bits of MBISTDCTL,
except MBISTDCTL[1:0], must be
kept LOW. Only bits[19:0] of MBISTDIN and MBISTDOUT are used.
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