5.2.5. MBIST testing of the cache controller dirty RAM
There is one dirty RAM associated with the cache controller.
The dirty RAM uses the same address as the tag RAMs. Table 5.5 shows the address
range of MBISTADDR used to test
the dirty RAM, based on the cache controller size.
Table 5.5. MBISTADDR and MBISTIDIN mappings for dirty RAM
| Size | Number of dirty RAM Indexes | MBISTADDR to dirty RAM mapping | MBISTDIN to dirty RAM mapping |
|---|
| 128KB | 512 | TAGADDR[8:0] = MBISTADDR[10:2] | DIRTYWD[15:0] = MBISTDIN[15:0] |
| 256KB | 1 024 | TAGADDR[9:0] = MBISTADDR[11:2] | DIRTYWD[15:0] = MBISTDIN[15:0] |
| 512KB | 2 048 | TAGADDR[10:0] = MBISTADDR[12:2] | DIRTYWD[15:0] = MBISTDIN[15:0] |
| 1MB | 4 096 | TAGADDR[11:0] = MBISTADDR[13:2] | DIRTYWD[15:0] = MBISTDIN[15:0] |
| 2MB | 8 192 | TAGADDR[12:0] = MBISTADDR[14:2] | DIRTYWD[15:0] = MBISTDIN[15:0] |
The data from the dirty RAM is always registered by the cache
controller. In addition, there is a register on the MBIST port of
the cache controller. So, to the cache controller MBIST controller,
the cache controller always adds two register delays to the MBIST data
read path for the dirty RAM. The latency can be from one to eight
clock cycles as described in MBIST compiled RAM latencies.
Figure 5.5 shows
the paths for dirty RAM testing using MBIST.
In Figure 5.5 MBISTCE[9] is for the write enable
to the dirty RAM. MBISTCE[9] corresponds
to DIRTYCS. MBISTDCTL[11] is
for reads from previous MBIST transactions. MBISTDCTL[11] must
be set to 1 and MBISTDCTL[12, 10:2] must
be set to 0 to select the dirty RAM read data on the cycle that
the read data is valid at the output of the RAM. The dirty RAM uses
the same address as the tag RAM.
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