L210 Cache Controller Technical Reference Manual

Revision r0p5

Table of Contents

About this manual
Product revision status
Intended audience
Using this manual
Further reading
Feedback on this product
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1. Introduction
1.1. About the Cache Controller
1.2. Cache controller block diagram
1.2.1. Operating frequency
1.3. Functional description
1.3.1. Features
1.3.2. Buffers
1.3.3. Error support and MBIST support
1.3.4. Event bus
1.3.5. Configuring the cache controller
1.4. Supported ARM architectures
1.5. L210 Cache Controller product revisions
2. Programmer’s Model
2.1. ARM register fields
2.2. About the cache controller registers
2.3. Register summary
2.3.1. ID Register
2.3.2. Cache Type Register
2.3.3. Control Register
2.3.4. Auxiliary Control Register
2.3.5. Cache maintenance operations
2.3.6. Register 9: Cache Lockdown
2.3.7. Uses of Lockdown Format C
2.4. Replacement strategy
2.5. Register 15: Test and Debug
2.5.1. Debug Control Register
2.6. Buffers
2.6.1. Write buffer
2.6.2. Write-allocate buffer
2.6.3. Eviction buffer
2.7. Ports configuration
2.8. Hazards
2.8.1. L2 hazards handled internally
2.9. External abort support for L3 memory
3. RAM Interfaces
3.1. About RAM interfaces
3.2. RAM configuration versus associativity and way size
3.2.1. Data RAM
3.2.2. Tag RAM
3.2.3. Dirty RAM
3.3. Data RAM
3.4. Tag RAM
3.5. Dirty RAM
4. Using the Cache Controller
4.1. Configuring the cache controller
4.1.1. Sizes and associativity
4.1.2. Compiled RAM latency
4.1.3. Eviction and linefill buffers
4.1.4. Cache Sync
4.1.5. Asynchronous interface
4.1.6. Asynchronous interface control
4.2. Clocking
4.3. Idle
4.4. Disabled
4.5. Set-up sequence
4.6. Behavior for ARMv5 memory systems
4.6.1. ARMv5 system transactions
4.6.2. Behavior for ARMv5 transactions
4.7. Behavior for ARMv6 memory systems
4.7.1. ARMv6 system transactions
4.7.2. Behavior for ARMv6 transactions
4.7.4. Locked and exclusive access
4.8. Timing diagrams
4.8.1. Hit
4.8.2. Miss
4.8.3. Two simultaneous hits
4.8.4. Buffered write
4.8.5. Outer noncacheable access
5. Design for Test
5.1. About design for test
5.2. Memory built-in self-test, MBIST
5.2.1. MBIST compiled RAM latencies
5.2.2. MBIST testing of cache controller data RAM
5.2.3. MBIST testing of cache controller data parity RAM
5.2.4. MBIST testing of the cache controller tag RAMs
5.2.5. MBIST testing of the cache controller dirty RAM
6. Parity and RAM Error Support
6.1. Parity and RAM error support
6.2. Error signaling and handling
A. Signal Descriptions
A.1. Cache controller signals
A.1.1. Slave port 0 signals
A.1.2. Master port 0 signals
A.1.3. Slave port 1 signals
A.1.4. Master port 1 signals
A.1.5. Slave port 2 signals
A.1.6. Master port 2 signals
A.1.7. Data RAM interface signals
A.1.8. Tag RAM interface signals
A.1.9. Dirty RAM interface signals
A.1.10. Cache controller event bus
A.1.11. Cache controller MBIST interface
A.1.12. Miscellaneous signals
B. AC Parameters
B.1. Cache controller interface signal timing parameters
B.1.1. Registered signals
B.1.2. Unregistered signals
C. Event Monitor
C.1. Cache controller event monitor
C.2. Programmer’s model
C.2.1. Event Monitor Control Register, EMMC
C.2.2. Counter Status Register, EMCS
C.2.3. Counter Configuration Registers, EMCCx
C.2.4. Event sources encodings
C.3. Implementation details
C.3.1. Event monitor clocking
C.3.2. Interrupts
C.3.3. AHB clocking
C.3.4. AHB-Lite slave port interface signals
C.4. Event monitor signals
D. Master and Slave Port Configurations
D.1. ARM1136 memory system configurations
D.2. ARM926EJ-S and ARM1026EJ-S memory systems
D.3. Mapping of slave to master port bursts
D.3.1. L2 off or noncacheable read accesses
D.3.2. L2 off or nonbufferable write accesses

List of Tables

1.1. Typical memory sizes and access times
1.2. Transactions for a three-master port system
1.3. Transactions for a two-master port system
1.4. Transactions for a single-master port system
2.1. Summary register map
2.2. Register map
2.3. ID Register encoding
2.4. Release number index values and releases
2.5. Cache Type Register
2.6. Control Register
2.7. Auxiliary Control Register
2.8. Cache maintenance operations
2.9. Writing or reading register to way bits
2.10. Line Tag Register mapping
2.11. Debug Control Register
3.1. Cache associativity and bits[15:13] of data RAM bus address
3.2. Way size and bits[12:0] of data RAM bus address
3.3. Tag RAM and way size
3.4. Way size and TAGADDR values
3.5. Associativity and DIRTYRD and DIRTYWD values
3.6. Values for N in RAM size diagrams
4.1. Total cache size compared to way size and associativity
4.2. Asynchronous mode control pins
4.3. HPROTSx[4:2] and TLB correspondences in an ARMv5 system
4.4. Behavior for ARMv5 transactions
4.5. HPROTSx[4-2] and TLB correspondences in ARMv6
4.6. Behavior with ARMv6 memory types
4.7. Example uses of HBSTRBSx and HUNALIGNSx, little-endian
5.1. Using MBISTADDR as an index for data RAM writes
5.2. MBISTADDR and MBISTDIN mappings for data RAM
5.3. MBISTADDR and MBISTDIN mappings for data parity RAM
5.4. MBISTADDR and MBISTDIN mapping for Tag RAMs
5.5. MBISTADDR and MBISTIDIN mappings for dirty RAM
A.1. Slave port 0 signals
A.2. Master port 0 signals
A.3. Slave port 1 signals
A.4. Master port 1 signals
A.5. Slave port 2 signals
A.6. Master port 2 signals
A.7. Data RAM interface signals
A.8. Tag RAM interface signals
A.9. Dirty RAM interface signals
A.10. Cache controller event bus output signals
A.11. Cache controller MBIST block inputs and outputs
A.12. Miscellaneous signals
C.1. Event monitor registers
C.2. EMMC bit fields descriptions
C.3. Counter Status Register
C.4. Counter Configuration Register
C.5. Event sources encodings
C.6. AHB-Lite slave port interface signals
C.7. Event monitor input signals
D.1. WRAPn read access conversions on slave ports

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Confidentiality Status

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision AMay 2003For Limited release
Revision BJune 2003Final, r0p1, latency signals added, Appendix E added
Revision COctober 2003R0p2. Product name corrected, Configurability of master and slave ports clarified, Figure 4-5, L210 Miss, redrawn, Section 5.2 rewritten, LRB1 replaces LRB 0 as MBIST, HMASTERMx signal descriptions corrected, Appendix E extended to cover ARM 7 cores and ARM 9 coresGlossary updated, extended and corrected.
Revision D23 April 2004R0p3 updates. Minor modifications to register map and cache maintenance tables. Additional comments to Cache Sync maintenance operation. Preventing or reducing cache pollution section rewritten. Sections on L210 Clocking, Idle, disabled states moved to chapter 4. Comments added to section 4.6.1 concerning additional piece of hardware provided.Additional comments to unaligned burst accesses and known length bursts in section 4.6.2. Default value for HMASTERM0 removed. Additional comments for HMASTERM1, HMASTERM2, HPROTMx, HSIDEBANDx signals. Additional appendix section D3 Mapping of slave to master port bursts. Section E.2.1 program listing corrected.Section E.2.2 only relevant to ARM926 revisions r0p0-r0p4, fixed from r0p5
Revision E27 May 2005R0p4 updates.Section 1.5 corrected. Section 2.2 Introductory text to Table 2-1 clarified. Table 2-4 added. Section 2.3.5 Description of background operations clarified.
Revision F19 September 2005R0p5 updates. Table 2-4 updated. Section 4.1.4 Cache Sync rewritten.
Revision G20 September 2006Event Monitor text clarified.Product renamed to become ARM PrimeCell L210 Level 2 Cache Controller.Section 3.2 removed. Table C‑5 on page C‑7 rewritten for clarity.Appendix E replaced by Applications Note Using the L210 Cache Controller with ARM7 and ARM9 cores (ARM DAI 0169A)Table A‑10 on page A‑13 footnote reworded.
Copyright © 2003-2006 ARM Limited. All rights reserved.ARM DDI 0284G