Using this manual

This manual is organized into the following chapters:

Chapter 1 Introduction

Read this chapter for an introduction to the functionality of the cache controller.

Chapter 2 Programmer’s Model

Read this chapter for a description of the cache controller registers and for programming details.

Chapter 3 RAM Interfaces

Read this chapter for details of the RAM interfaces.

Chapter 4 Using the Cache Controller

Read this chapter for details of how to use the cache controller effectively.

Chapter 5 Design for Test

Read this chapter for details of the L210 features that help with design for test issues.

Chapter 6 Parity and RAM Error Support

Read this chapter for details of the parity and RAM error support.

Appendix A Signal Descriptions

Read this appendix for a description of the signals used in the cache controller.

Appendix B AC Parameters

Read this appendix for a description of the AC timing parameters of the cache controller signals.

Appendix C Event Monitor

Read this appendix for a description of the cache controller event monitor block.

Appendix D Master and Slave Port Configurations

Read this appendix for a description of the different master and slave port configurations of the cache controller.

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