3.1.1. About the bus architecture

The ARM926PXP development chip peripherals are interconnected to enable maximum flexibility in the final SoC performance by extensive use of multilayer Advanced High-performance Bus (AHB). The multilayer AHB architecture provides a performance advantage by enabling multiple bus masters to be active in parallel. For example, the DMAC can transfer data to the UART, while the CLCDC fetches data from the MPMC and the ARM processor accesses the Timer modules.

Six AHB buses are provided:

ARM I AHB

This bus is used by the instruction fetch port of the ARM926EJ-S processor and has access to the memory interfaces. This AHB supports external bus slaves.

ARM D AHB

This bus is used by the data bus port of the ARM926EJ-S processor and has access to all of the ARM926PXP development chip peripherals. This AHB supports external bus slaves.

CLCDC AHB

This bus is used by the ARM926PXP development chip CLCDC to fetch display data from either of the memory interfaces. The AHB supports external bus slaves.

DMA0 AHB

This bus is used for DMA peripheral accesses and is connected to the DMA APB bridge. External bus slaves are supported.

DMA1 AHB

This bus is used for DMA memory accesses and is connected to the memory interfaces. External bus slaves are supported.

Expansion AHB

An expansion AHB bus supports the external M1 and M2 master buses and the S slave bus.

Two Advanced Peripheral Buses (APBs) are provided. They are:

DMA APB

This bus is used to access the APB peripherals that are required to support DMA transfers. This APB supports external APB expansion with 11 external APB select lines provided.

Core APB

This bus is used to access the APB peripherals that are required by the ARM926EJ-S processor.

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