18.4.2. Flush-to-Zero mode

Setting the FZ bit, FPSCR[24], enables Flush-to-Zero mode and increases performance on very small inputs and results. In Flush-to-Zero mode, the VFP9-S coprocessor treats all subnormal input operands of arithmetic CDP operations as positive zeros in the operation. Exceptions that result from a zero operand are signaled appropriately. FABS, FCMP, and FNEG are not considered arithmetic CDP operations, and are not affected by Flush-to-Zero mode. A result that is tiny, as described in the IEEE 754 standard, for the destination precision is smaller in magnitude than the minimum normal value before rounding and is replaced with a positive zero. The IDC flag, FPSCR[7], indicates when an input flush occurs. The UFC flag, FPSCR[3], indicates when a result flush occurs.

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