3.1.5. Endianness

The ARM926PXP development chip supports both little-endian and big-endian operation. The endianness required is configured using bit 7 of Register 1 of CP15 in the ARM926EJ-S system control coprocessor. The ARM926PXP development chip provides the BIGENDOUT output signal so that components outside the ARM926PXP development chip can also be configured for endianness using this control.

Following a reset, the ARM926PXP development chip defaults to the endianness defined by the CFGCPUBIGENDIN input signal (this signal connects to the internal BIGENDINIT signal). The B-bit in the ARM926EJ-S CP15 r1 Register is set to the same state as BIGENDINIT at the time of reset. When BIGENDINIT=0 then little-endian mode is selected.

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