7.1. About the ARM MBX HR-S

The ARM MBX HR-S is an Advanced Microcontroller Bus Architecture (AMBA) compliant System-on-a-Chip (SoC) component. Figure 7.1 shows a top-level block diagram of the ARM MBX HR-S. The MBX component connects directly to the MPMC and the AHB bus matrix.

Figure 7.1. ARM MBX HR-S top level block diagram

The ARM MBX consists of the following modules:

The release version used is r1p2. The base address for the MBX registers is 0x40000000. The modules are described in more detail in the ARM MBX HR-S Graphics Core Technical Reference Manual.

The ARM MBX HR-S operates on 3D scene data (sent as batches of triangles) that are transformed and lit either by the Central Processing Unit (CPU) or by the VGP. Triangles are written directly to the TA on a First In First Out (FIFO) basis so that the CPU is not stalled. The TA performs advanced culling on triangle data by writing the tiled non-culled triangles to the external memory.

The event manager uses SmartBuffer technology so that any level of scene complexity can be handled in a fixed buffer size.

The HSR engine reads the tiled data and implements per-pixel HSR with full Z-accuracy. The resulting visible pixels are textured and shaded in Internal True Color (ITC) before rendering the final image for display.


The ARM MBX HR-S has the following interfaces:

  • the register block interface is an AMBA Advanced High-performance Bus (AHB) slave interface

  • the memory interface is a simple handshake protocol that is defined as the MBX memory interface.

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