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Table A.1 lists the pad signals and the signal characteristics:
The Function column identifies the major functional block.
The Type column indicates the signal direction:
Input
Input with internal pull-up
Output
Bidirectional I/O
Tristate output
Power to I/O
Power to core.
The Drive column indicates the drive strength in mA.
The BGA column is the pad identifier.
BGA pads not listed are ground. See Figure B.1 for more information on pin numbering and layout.
Table A.1. Pad signals
| Function | Signal | Description | Type | Drive | BGA |
|---|---|---|---|---|---|
| AHB M1 | HADDRM1[0] | Address bus | T | 8 | AK31 |
| AHB M1 | HADDRM1[1] | Address bus | T | 8 | AK32 |
| AHB M1 | HADDRM1[2] | Address bus | T | 8 | AG30 |
| AHB M1 | HADDRM1[3] | Address bus | T | 8 | AK33 |
| AHB M1 | HADDRM1[4] | Address bus | T | 8 | AG29 |
| AHB M1 | HADDRM1[5] | Address bus | T | 8 | AK34 |
| AHB M1 | HADDRM1[6] | Address bus | T | 8 | AE28 |
| AHB M1 | HADDRM1[7] | Address bus | T | 8 | AJ31 |
| AHB M1 | HADDRM1[8] | Address bus | T | 8 | AJ32 |
| AHB M1 | HADDRM1[9] | Address bus | T | 8 | AJ33 |
| AHB M1 | HADDRM1[10] | Address bus | T | 8 | AF30 |
| AHB M1 | HADDRM1[11] | Address bus | T | 8 | AH31 |
| AHB M1 | HADDRM1[12] | Address bus | T | 8 | AE30 |
| AHB M1 | HADDRM1[13] | Address bus | T | 8 | AH32 |
| AHB M1 | HADDRM1[14] | Address bus | T | 8 | AF29 |
| AHB M1 | HADDRM1[15] | Address bus | T | 8 | AH33 |
| AHB M1 | HADDRM1[16] | Address bus | T | 8 | AH34 |
| AHB M1 | HADDRM1[17] | Address bus | T | 8 | AG31 |
| AHB M1 | HADDRM1[18] | Address bus | T | 8 | AE29 |
| AHB M1 | HADDRM1[19] | Address bus | T | 8 | AG32 |
| AHB M1 | HADDRM1[20] | Address bus | T | 8 | AD29 |
| AHB M1 | HADDRM1[21] | Address bus | T | 8 | AG33 |
| AHB M1 | HADDRM1[22] | Address bus | T | 8 | AD30 |
| AHB M1 | HADDRM1[23] | Address bus | T | 8 | AG34 |
| AHB M1 | HADDRM1[24] | Address bus | T | 8 | AF31 |
| AHB M1 | HADDRM1[25] | Address bus | T | 8 | AF32 |
| AHB M1 | HADDRM1[26] | Address bus | T | 8 | AD28 |
| AHB M1 | HADDRM1[27] | Address bus | T | 8 | AF33 |
| AHB M1 | HADDRM1[28] | Address bus | T | 8 | AC28 |
| AHB M1 | HADDRM1[29] | Address bus | T | 8 | AF34 |
| AHB M1 | HADDRM1[30] | Address bus | T | 8 | AC29 |
| AHB M1 | HADDRM1[31] | Address bus | T | 8 | AE33 |
| AHB M1 | HBURSTM1[0] | Transfer burst length | T | 8 | AD33 |
| AHB M1 | HBURSTM1[1] | Transfer burst length | T | 8 | AB29 |
| AHB M1 | HBURSTM1[2] | Transfer burst length | T | 8 | AD34 |
| AHB M1 | HBUSREQM1 | Master bus request | O | 8 | AL32 |
| AHB M1 | HDATAM1[0] | Data bus | B | 8 | AB32 |
| AHB M1 | HDATAM1[1] | Data bus | B | 8 | AB33 |
| AHB M1 | HDATAM1[2] | Data bus | B | 8 | AB34 |
| AHB M1 | HDATAM1[3] | Data bus | B | 8 | Y28 |
| AHB M1 | HDATAM1[4] | Data bus | B | 8 | AA31 |
| AHB M1 | HDATAM1[5] | Data bus | B | 8 | Y29 |
| AHB M1 | HDATAM1[6] | Data bus | B | 8 | AA32 |
| AHB M1 | HDATAM1[7] | Data bus | B | 8 | Y30 |
| AHB M1 | HDATAM1[8] | Data bus | B | 8 | AA33 |
| AHB M1 | HDATAM1[9] | Data bus | B | 8 | AA30 |
| AHB M1 | HDATAM1[10] | Data bus | B | 8 | Y31 |
| AHB M1 | HDATAM1[11] | Data bus | B | 8 | Y32 |
| AHB M1 | HDATAM1[12] | Data bus | B | 8 | Y33 |
| AHB M1 | HDATAM1[13] | Data bus | B | 8 | W28 |
| AHB M1 | HDATAM1[14] | Data bus | B | 8 | Y34 |
| AHB M1 | HDATAM1[15] | Data bus | B | 8 | W29 |
| AHB M1 | HDATAM1[16] | Data bus | B | 8 | W32 |
| AHB M1 | HDATAM1[17] | Data bus | B | 8 | W33 |
| AHB M1 | HDATAM1[18] | Data bus | B | 8 | W34 |
| AHB M1 | HDATAM1[19] | Data bus | B | 8 | V29 |
| AHB M1 | HDATAM1[20] | Data bus | B | 8 | V31 |
| AHB M1 | HDATAM1[21] | Data bus | B | 8 | W30 |
| AHB M1 | HDATAM1[22] | Data bus | B | 8 | V33 |
| AHB M1 | HDATAM1[23] | Data bus | B | 8 | V28 |
| AHB M1 | HDATAM1[24] | Data bus | B | 8 | U33 |
| AHB M1 | HDATAM1[25] | Data bus | B | 8 | V30 |
| AHB M1 | HDATAM1[26] | Data bus | B | 8 | U32 |
| AHB M1 | HDATAM1[27] | Data bus | B | 8 | U28 |
| AHB M1 | HDATAM1[28] | Data bus | B | 8 | U31 |
| AHB M1 | HDATAM1[29] | Data bus | B | 8 | T34 |
| AHB M1 | HDATAM1[30] | Data bus | B | 8 | T33 |
| AHB M1 | HDATAM1[31] | Data bus | B | 8 | U29 |
| AHB M1 | HGRANTM1 | Arbiter bus grant | I | - | AJ30 |
| AHB M1 | HLOCKM1 | Locked sequence | O | 8 | AF28 |
| AHB M1 | HPROTM1[0] | Protection Control | T | 8 | AC31 |
| AHB M1 | HPROTM1[1] | Protection Control | T | 8 | AC32 |
| AHB M1 | HPROTM1[2] | Protection Control | T | 8 | AA28 |
| AHB M1 | HPROTM1[3] | Protection Control | T | 8 | AC33 |
| AHB M1 | HREADYM1 | Transfer finished | I | - | AA29 |
| AHB M1 | HRESPM1[0] | Transfer response | I | - | AC34 |
| AHB M1 | HRESPM1[1] | Transfer response | I | - | AB30 |
| AHB M1 | HSIZEM1[0] | Transfer size | T | 8 | AD32 |
| AHB M1 | HSIZEM1[1] | Transfer size | T | 8 | AC30 |
| AHB M1 | HTRANSM1[0] | Transfer type | T | 8 | AD31 |
| AHB M1 | HTRANSM1[1] | Transfer type | T | 8 | AB28 |
| AHB M1 | HWRITEM1 | Write transfer | T | 8 | AE34 |
| AHB M2 | HADDRM2[0] | Address bus | T | 8 | N32 |
| AHB M2 | HADDRM2[1] | Address bus | T | 8 | M34 |
| AHB M2 | HADDRM2[2] | Address bus | T | 8 | M33 |
| AHB M2 | HADDRM2[3] | Address bus | T | 8 | R28 |
| AHB M2 | HADDRM2[4] | Address bus | T | 8 | M32 |
| AHB M2 | HADDRM2[5] | Address bus | T | 8 | P30 |
| AHB M2 | HADDRM2[6] | Address bus | T | 8 | M31 |
| AHB M2 | HADDRM2[7] | Address bus | T | 8 | P29 |
| AHB M2 | HADDRM2[8] | Address bus | T | 8 | L34 |
| AHB M2 | HADDRM2[9] | Address bus | T | 8 | L33 |
| AHB M2 | HADDRM2[10] | Address bus | T | 8 | L32 |
| AHB M2 | HADDRM2[11] | Address bus | T | 8 | P28 |
| AHB M2 | HADDRM2[12] | Address bus | T | 8 | L31 |
| AHB M2 | HADDRM2[13] | Address bus | T | 8 | N30 |
| AHB M2 | HADDRM2[14] | Address bus | T | 8 | K34 |
| AHB M2 | HADDRM2[15] | Address bus | T | 8 | N29 |
| AHB M2 | HADDRM2[16] | Address bus | T | 8 | K32 |
| AHB M2 | HADDRM2[17] | Address bus | T | 8 | N28 |
| AHB M2 | HADDRM2[18] | Address bus | T | 8 | J34 |
| AHB M2 | HADDRM2[19] | Address bus | T | 8 | J33 |
| AHB M2 | HADDRM2[20] | Address bus | T | 8 | J32 |
| AHB M2 | HADDRM2[21] | Address bus | T | 8 | M30 |
| AHB M2 | HADDRM2[22] | Address bus | T | 8 | J31 |
| AHB M2 | HADDRM2[23] | Address bus | T | 8 | M28 |
| AHB M2 | HADDRM2[24] | Address bus | T | 8 | H34 |
| AHB M2 | HADDRM2[25] | Address bus | T | 8 | H33 |
| AHB M2 | HADDRM2[26] | Address bus | T | 8 | H32 |
| AHB M2 | HADDRM2[27] | Address bus | T | 8 | M29 |
| AHB M2 | HADDRM2[28] | Address bus | T | 8 | H31 |
| AHB M2 | HADDRM2[29] | Address bus | T | 8 | L30 |
| AHB M2 | HADDRM2[30] | Address bus | T | 8 | G34 |
| AHB M2 | HADDRM2[31] | Address bus | T | 8 | L28 |
| AHB M2 | HBURSTM2[0] | Transfer burst length | T | 8 | L29 |
| AHB M2 | HBURSTM2[1] | Transfer burst length | T | 8 | F33 |
| AHB M2 | HBURSTM2[2] | Transfer burst length | T | 8 | K29 |
| AHB M2 | HBUSREQM2 | Master bus request | O | 8 | T28 |
| AHB M2 | HDATAM2[0] | Data bus | B | 8 | J28 |
| AHB M2 | HDATAM2[1] | Data bus | B | 8 | E34 |
| AHB M2 | HDATAM2[2] | Data bus | B | 8 | E33 |
| AHB M2 | HDATAM2[3] | Data bus | B | 8 | E32 |
| AHB M2 | HDATAM2[4] | Data bus | B | 8 | J29 |
| AHB M2 | HDATAM2[5] | Data bus | B | 8 | E31 |
| AHB M2 | HDATAM2[6] | Data bus | B | 8 | H30 |
| AHB M2 | HDATAM2[7] | Data bus | B | 8 | D32 |
| AHB M2 | HDATAM2[8] | Data bus | B | 8 | H29 |
| AHB M2 | HDATAM2[9] | Data bus | B | 8 | F28 |
| AHB M2 | HDATAM2[10] | Data bus | B | 8 | C31 |
| AHB M2 | HDATAM2[11] | Data bus | B | 8 | D30 |
| AHB M2 | HDATAM2[12] | Data bus | B | 8 | G28 |
| AHB M2 | HDATAM2[13] | Data bus | B | 8 | F27 |
| AHB M2 | HDATAM2[14] | Data bus | B | 8 | F29 |
| AHB M2 | HDATAM2[15] | Data bus | B | 8 | G27 |
| AHB M2 | HDATAM2[16] | Data bus | B | 8 | C30 |
| AHB M2 | HDATAM2[17] | Data bus | B | 8 | E27 |
| AHB M2 | HDATAM2[18] | Data bus | B | 8 | B30 |
| AHB M2 | HDATAM2[19] | Data bus | B | 8 | A30 |
| AHB M2 | HDATAM2[20] | Data bus | B | 8 | E29 |
| AHB M2 | HDATAM2[21] | Data bus | B | 8 | F26 |
| AHB M2 | HDATAM2[22] | Data bus | B | 8 | D29 |
| AHB M2 | HDATAM2[23] | Data bus | B | 8 | E26 |
| AHB M2 | HDATAM2[24] | Data bus | B | 8 | C29 |
| AHB M2 | HDATAM2[25] | Data bus | B | 8 | G26 |
| AHB M2 | HDATAM2[26] | Data bus | B | 8 | B29 |
| AHB M2 | HDATAM2[27] | Data bus | B | 8 | A29 |
| AHB M2 | HDATAM2[28] | Data bus | B | 8 | E28 |
| AHB M2 | HDATAM2[29] | Data bus | B | 8 | G25 |
| AHB M2 | HDATAM2[30] | Data bus | B | 8 | D28 |
| AHB M2 | HDATAM2[31] | Data bus | B | 8 | E25 |
| AHB M2 | HGRANTM2 | Arbiter bus grant | I | - | R29 |
| AHB M2 | HLOCKM2 | Locked sequence | O | 8 | N33 |
| AHB M2 | HPROTM2[0] | Protection Control | T | 8 | F32 |
| AHB M2 | HPROTM2[1] | Protection Control | T | 8 | F31 |
| AHB M2 | HPROTM2[2] | Protection Control | T | 8 | F30 |
| AHB M2 | HPROTM2[3] | Protection Control | T | 8 | K28 |
| AHB M2 | HREADYM2 | Transfer finished | I | - | G29 |
| AHB M2 | HRESPM2[0] | Transfer response | I | - | J30 |
| AHB M2 | HRESPM2[1] | Transfer response | I | - | H28 |
| AHB M2 | HSIZEM2[0] | Transfer size | T | 8 | K30 |
| AHB M2 | HSIZEM2[1] | Transfer size | T | 8 | F34 |
| AHB M2 | HTRANSM2[0] | Transfer type | T | 8 | G32 |
| AHB M2 | HTRANSM2[1] | Transfer type | T | 8 | G31 |
| AHB M2 | HWRITEM2 | Write transfer | T | 8 | G33 |
| AHB S | HADDRS[0] | Address bus | I | - | D7 |
| AHB S | HADDRS[1] | Address bus | I | - | F10 |
| AHB S | HADDRS[2] | Address bus | I | - | A6 |
| AHB S | HADDRS[3] | Address bus | I | - | G10 |
| AHB S | HADDRS[4] | Address bus | I | - | B6 |
| AHB S | HADDRS[5] | Address bus | I | - | E9 |
| AHB S | HADDRS[6] | Address bus | I | - | C6 |
| AHB S | HADDRS[7] | Address bus | I | - | F9 |
| AHB S | HADDRS[8] | Address bus | I | - | D6 |
| AHB S | HADDRS[9] | Address bus | I | - | G9 |
| AHB S | HADDRS[10] | Address bus | I | - | A5 |
| AHB S | HADDRS[11] | Address bus | I | - | H5 |
| AHB S | HADDRS[12] | Address bus | I | - | E4 |
| AHB S | HADDRS[13] | Address bus | I | - | J7 |
| AHB S | HADDRS[14] | Address bus | I | - | E3 |
| AHB S | HADDRS[15] | Address bus | I | - | E2 |
| AHB S | HADDRS[16] | Address bus | I | - | E1 |
| AHB S | HADDRS[17] | Address bus | I | - | J5 |
| AHB S | HADDRS[18] | Address bus | I | - | G6 |
| AHB S | HADDRS[19] | Address bus | I | - | J6 |
| AHB S | HADDRS[20] | Address bus | I | - | F5 |
| AHB S | HADDRS[21] | Address bus | I | - | K7 |
| AHB S | HADDRS[22] | Address bus | I | - | F4 |
| AHB S | HADDRS[23] | Address bus | I | - | K6 |
| AHB S | HADDRS[24] | Address bus | I | - | F3 |
| AHB S | HADDRS[25] | Address bus | I | - | K5 |
| AHB S | HADDRS[26] | Address bus | I | - | F1 |
| AHB S | HADDRS[27] | Address bus | I | - | L7 |
| AHB S | HADDRS[28] | Address bus | I | - | G5 |
| AHB S | HADDRS[29] | Address bus | I | - | L6 |
| AHB S | HADDRS[30] | Address bus | I | - | G4 |
| AHB S | HADDRS[31] | Address bus | I | - | G3 |
| AHB S | HBURSTS[0] | Transfer burst length | I | - | M6 |
| AHB S | HBURSTS[1] | Transfer burst length | I | - | H3 |
| AHB S | HBURSTS[2] | Transfer burst length | I | - | M5 |
| AHB S | HDATAS[0] | Data bus | B | 8 | B13 |
| AHB S | HDATAS[1] | Data bus | B | 8 | F15 |
| AHB S | HDATAS[2] | Data bus | B | 8 | C13 |
| AHB S | HDATAS[3] | Data bus | B | 8 | G15 |
| AHB S | HDATAS[4] | Data bus | B | 8 | A12 |
| AHB S | HDATAS[5] | Data bus | B | 8 | F14 |
| AHB S | HDATAS[6] | Data bus | B | 8 | B12 |
| AHB S | HDATAS[7] | Data bus | B | 8 | C12 |
| AHB S | HDATAS[8] | Data bus | B | 8 | D12 |
| AHB S | HDATAS[9] | Data bus | B | 8 | E13 |
| AHB S | HDATAS[10] | Data bus | B | 8 | B11 |
| AHB S | HDATAS[11] | Data bus | B | 8 | G14 |
| AHB S | HDATAS[12] | Data bus | B | 8 | C11 |
| AHB S | HDATAS[13] | Data bus | B | 8 | F13 |
| AHB S | HDATAS[14] | Data bus | B | 8 | D11 |
| AHB S | HDATAS[15] | Data bus | B | 8 | A10 |
| AHB S | HDATAS[16] | Data bus | B | 8 | B10 |
| AHB S | HDATAS[17] | Data bus | B | 8 | G13 |
| AHB S | HDATAS[18] | Data bus | B | 8 | C10 |
| AHB S | HDATAS[19] | Data bus | B | 8 | G12 |
| AHB S | HDATAS[20] | Data bus | B | 8 | A9 |
| AHB S | HDATAS[21] | Data bus | B | 8 | E12 |
| AHB S | HDATAS[22] | Data bus | B | 8 | B9 |
| AHB S | HDATAS[23] | Data bus | B | 8 | F12 |
| AHB S | HDATAS[24] | Data bus | B | 8 | C9 |
| AHB S | HDATAS[25] | Data bus | B | 8 | D9 |
| AHB S | HDATAS[26] | Data bus | B | 8 | A8 |
| AHB S | HDATAS[27] | Data bus | B | 8 | E11 |
| AHB S | HDATAS[28] | Data bus | B | 8 | B8 |
| AHB S | HDATAS[29] | Data bus | B | 8 | G11 |
| AHB S | HDATAS[30] | Data bus | B | 8 | D8 |
| AHB S | HDATAS[31] | Data bus | B | 8 | F11 |
| AHB S | HMASTLOCKS | Locked sequence | I | - | J3 |
| AHB S | HPROTS[0] | Protection Control | I | - | H2 |
| AHB S | HPROTS[1] | Protection Control | I | - | N7 |
| AHB S | HPROTS[2] | Protection Control | I | - | H1 |
| AHB S | HPROTS[3] | Protection Control | I | - | N6 |
| AHB S | HREADYS | Transfer finished | B | 8 | E10 |
| AHB S | HRESPS[0] | Transfer response | T | 8 | B7 |
| AHB S | HRESPS[1] | Transfer response | T | 8 | C7 |
| AHB S | HSELS | Slave select | I | - | N5 |
| AHB S | HSIZES[0] | Transfer size | I | - | L5 |
| AHB S | HSIZES[1] | Transfer size | I | - | H4 |
| AHB S | HTRANSS[0] | Transfer type | I | - | M7 |
| AHB S | HTRANSS[1] | Transfer type | I | - | G1 |
| AHB S | HWRITES | Write transfer | I | - | G2 |
| AHB Monitor | AHBMONITOR[0] | Debug information | O | 8 | F25 |
| AHB Monitor | AHBMONITOR[1] | Debug information | O | 8 | B28 |
| AHB Monitor | AHBMONITOR[2] | Debug information | O | 8 | G24 |
| AHB Monitor | AHBMONITOR[3] | Debug information | O | 8 | D27 |
| AHB Monitor | AHBMONITOR[4] | Debug information | O | 8 | F24 |
| AHB Monitor | AHBMONITOR[5] | Debug information | O | 8 | C27 |
| AHB Monitor | AHBMONITOR[6] | Debug information | O | 8 | B27 |
| AHB Monitor | AHBMONITOR[7] | Debug information | O | 8 | A27 |
| AHB Monitor | AHBMONITOR[8] | Debug information | O | 8 | E24 |
| AHB Monitor | AHBMONITOR[9] | Debug information | O | 8 | D26 |
| AHB Monitor | AHBMONITOR[10] | Debug information | O | 8 | G23 |
| AHB Monitor | AHBMONITOR[11] | Debug information | O | 8 | C26 |
| AHB Monitor | AHBMONITOR[12] | Debug information | O | 8 | E23 |
| AHB Monitor | AHBMONITOR[13] | Debug information | O | 8 | B26 |
| AHB Monitor | AHBMONITOR[14] | Debug information | O | 8 | F23 |
| AHB Monitor | AHBMONITOR[15] | Debug information | O | 8 | A26 |
| AHB Monitor | AHBMONITOR[16] | Debug information | O | 8 | C25 |
| AHB Monitor | AHBMONITOR[17] | Debug information | O | 8 | B25 |
| AHB Monitor | AHBMONITOR[18] | Debug information | O | 8 | G22 |
| AHB Monitor | AHBMONITOR[19] | Debug information | O | 8 | A25 |
| AHB Monitor | AHBMONITOR[20] | Debug information | O | 8 | F22 |
| AHB Monitor | AHBMONITOR[21] | Debug information | O | 8 | C24 |
| AHB Monitor | AHBMONITOR[22] | Debug information | O | 8 | E22 |
| AHB Monitor | AHBMONITOR[23] | Debug information | O | 8 | B24 |
| AHB Monitor | AHBMONITOR[24] | Debug information | O | 8 | G21 |
| AHB Monitor | AHBMONITOR[25] | Debug information | O | 8 | A24 |
| AHB Monitor | AHBMONITOR[26] | Debug information | O | 8 | F21 |
| AHB Monitor | AHBMONITOR[27] | Debug information | O | 8 | D23 |
| AHB Monitor | AHBMONITOR[28] | Debug information | O | 8 | C23 |
| AHB Monitor | AHBMONITOR[29] | Debug information | O | 8 | B23 |
| AHB Monitor | AHBMONITOR[30] | Debug information | O | 8 | G20 |
| AHB Monitor | AHBMONITOR[31] | Debug information | O | 8 | A23 |
| AHB Monitor | AHBMONITOR[32] | Debug information | O | 8 | E21 |
| AHB Monitor | AHBMONITOR[33] | Debug information | O | 8 | B22 |
| CLCDC | CLAC | AC bias drive/data enable | O | 4 | AN23 |
| CLCDC | CLCDCLKEXT | External Clock input for CLCD | I | - | AN22 |
| CLCDC | CLCP | Panel clock | O | 4 | AP23 |
| CLCDC | CLD[0] | Data bus | O | 4 | AH20 |
| CLCDC | CLD[1] | Data bus | O | 4 | AM23 |
| CLCDC | CLD[2] | Data bus | O | 4 | AL23 |
| CLCDC | CLD[3] | Data bus | O | 4 | AP24 |
| CLCDC | CLD[4] | Data bus | O | 4 | AK21 |
| CLCDC | CLD[5] | Data bus | O | 4 | AN24 |
| CLCDC | CLD[6] | Data bus | O | 4 | AK22 |
| CLCDC | CLD[7] | Data bus | O | 4 | AL24 |
| CLCDC | CLD[8] | Data bus | O | 4 | AJ21 |
| CLCDC | CLD[9] | Data bus | O | 4 | AP25 |
| CLCDC | CLD[10] | Data bus | O | 4 | AH21 |
| CLCDC | CLD[11] | Data bus | O | 4 | AN25 |
| CLCDC | CLD[12] | Data bus | O | 4 | AJ22 |
| CLCDC | CLD[13] | Data bus | O | 4 | AM25 |
| CLCDC | CLD[14] | Data bus | O | 4 | AK23 |
| CLCDC | CLD[15] | Data bus | O | 4 | AP26 |
| CLCDC | CLD[16] | Data bus | O | 4 | AH22 |
| CLCDC | CLD[17] | Data bus | O | 4 | AN26 |
| CLCDC | CLD[18] | Data bus | O | 4 | AM26 |
| CLCDC | CLD[19] | Data bus | O | 4 | AL26 |
| CLCDC | CLD[20] | Data bus | O | 4 | AJ23 |
| CLCDC | CLD[21] | Data bus | O | 4 | AP27 |
| CLCDC | CLD[22] | Data bus | O | 4 | AH23 |
| CLCDC | CLD[23] | Data bus | O | 4 | AN27 |
| CLCDC | CLFP | Frame synch pulse | O | 4 | AJ20 |
| CLCDC | CLLE | Line end | O | 4 | AK24 |
| CLCDC | CLLP | Line synch pulse | O | 4 | AK20 |
| CLCDC | CLPOWER | Panel power enable | O | 4 | AM22 |
| Clock | HCLKM1 | Asynchronous AHB Clock In | I | - | T32 |
| Clock | HCLKM2 | Asynchronous AHB Clock In | I | - | C28 |
| Clock | HCLKS | Asynchronous AHB Clock In | I | - | A7 |
| Clock | nPLLRESET | PLL reset | I | - | H7 |
| Clock | PLLCLKEXT | Clock input from a PLL | I | - | F8 |
| Clock | PLLPWRDN | PLL power down | I | - | D3 |
| Clock | REFCLK32K | 32KHz Reference Clock | I | - | C5 |
| Clock | TIMCLKEXT | Timer Clock | I | - | F20 |
| Clock | XTALCLKEXT | Clock input from a crystal oscillator | I | - | B5 |
| CPU | DBGACK | Debug acknowledge | O | 4 | E17 |
| CPU | EDBGRQ | External Debug request | I | - | C19 |
| DMAC | DMACBREQ[0] | Burst Transfer Request | I | - | L2 |
| DMAC | DMACBREQ[1] | Burst Transfer Request | I | - | R5 |
| DMAC | DMACBREQ[2] | Burst Transfer Request | I | - | L1 |
| DMAC | DMACBREQ[3] | Burst Transfer Request | I | - | T6 |
| DMAC | DMACBREQ[4] | Burst Transfer Request | I | - | M4 |
| DMAC | DMACBREQ[5] | Burst Transfer Request | I | - | T7 |
| DMAC | DMACCLR[0] | Request Acknowledge Clear | O | 4 | J2 |
| DMAC | DMACCLR[1] | Request Acknowledge Clear | O | 4 | J1 |
| DMAC | DMACCLR[2] | Request Acknowledge Clear | O | 4 | K3 |
| DMAC | DMACCLR[3] | Request Acknowledge Clear | O | 4 | P7 |
| DMAC | DMACCLR[4] | Request Acknowledge Clear | O | 4 | K2 |
| DMAC | DMACCLR[5] | Request Acknowledge Clear | O | 4 | P5 |
| DMAC | DMACLBREQ[0] | Last Burst Transfer Request | I | - | N1 |
| DMAC | DMACLBREQ[1] | Last Burst Transfer Request | I | - | U5 |
| DMAC | DMACLBREQ[2] | Last Burst Transfer Request | I | - | P4 |
| DMAC | DMACLBREQ[3] | Last Burst Transfer Request | I | - | U7 |
| DMAC | DMACLBREQ[4] | Last Burst Transfer Request | I | - | P3 |
| DMAC | DMACLBREQ[5] | Last Burst Transfer Request | I | - | V5 |
| DMAC | DMACLSREQ[0] | Last Single Transfer Request | I | - | P2 |
| DMAC | DMACLSREQ[1] | Last Single Transfer Request | I | - | V6 |
| DMAC | DMACLSREQ[2] | Last Single Transfer Request | I | - | P1 |
| DMAC | DMACLSREQ[3] | Last Single Transfer Request | I | - | V7 |
| DMAC | DMACLSREQ[4] | Last Single Transfer Request | I | - | R4 |
| DMAC | DMACLSREQ[5] | Last Single Transfer Request | I | - | R3 |
| DMAC | DMACSREQ[0] | Single Transfer Request | I | - | M3 |
| DMAC | DMACSREQ[1] | Single Transfer Request | I | - | M2 |
| DMAC | DMACSREQ[2] | Single Transfer Request | I | - | M1 |
| DMAC | DMACSREQ[3] | Single Transfer Request | I | - | T5 |
| DMAC | DMACSREQ[4] | Single Transfer Request | I | - | N3 |
| DMAC | DMACSREQ[5] | Single Transfer Request | I | - | U6 |
| DMAC | DMACTC[0] | Terminal Count | O | 4 | K1 |
| DMAC | DMACTC[1] | Terminal Count | O | 4 | P6 |
| DMAC | DMACTC[2] | Terminal Count | O | 4 | L4 |
| DMAC | DMACTC[3] | Terminal Count | O | 4 | R7 |
| DMAC | DMACTC[4] | Terminal Count | O | 4 | L3 |
| DMAC | DMACTC[5] | Terminal Count | O | 4 | R6 |
| ETM | ETMEXTIN | Debug cross trigger support | I | - | E14 |
| ETM | ETMEXTOUT[0] | Debug cross trigger support | O | 12 | A14 |
| ETM | ETMEXTOUT[1] | Debug cross trigger support | O | 12 | B14 |
| ETM | ETMEXTOUT[2] | Debug cross trigger support | O | 12 | D14 |
| ETM | ETMEXTOUT[3] | Debug cross trigger support | O | 12 | A13 |
| ETM | PIPESTAT[0] | Pipeline Status | O | 12 | C18 |
| ETM | PIPESTAT[1] | Pipeline Status | O | 12 | F17 |
| ETM | PIPESTAT[2] | Pipeline Status | O | 12 | B18 |
| ETM | TRACECLK | Trace Clock | O | 12 | A19 |
| ETM | TRACEPKT[0] | Trace Packet | O | 12 | G17 |
| ETM | TRACEPKT[1] | Trace Packet | O | 12 | A17 |
| ETM | TRACEPKT[2] | Trace Packet | O | 12 | B17 |
| ETM | TRACEPKT[3] | Trace Packet | O | 12 | D17 |
| ETM | TRACEPKT[4] | Trace Packet | O | 12 | F16ETM |
| ETM | TRACEPKT[6] | Trace Packet | O | 12 | A16 |
| ETM | TRACEPKT[7] | Trace Packet | O | 12 | B16 |
| ETM | TRACEPKT[8] | Trace Packet | O | 12 | E16 |
| ETM | TRACEPKT[9] | Trace Packet | O | 12 | C16 |
| ETM | TRACEPKT[10] | Trace Packet | O | 12 | A15 |
| ETM | TRACEPKT[11] | Trace Packet | O | 12 | B15 |
| ETM | TRACEPKT[12] | Trace Packet | O | 12 | G16 |
| ETM | TRACEPKT[13] | Trace Packet | O | 12 | C15 |
| ETM | TRACEPKT[14] | Trace Packet | O | 12 | E15 |
| ETM | TRACEPKT[15] | Trace Packet | O | 12 | D15 |
| ETM | TRACESYNC | Trace Sync | O | 12 | D18 |
| GPIO 0 | GP0[0] | General Purpose I/O | B | 8 | AF6 |
| GPIO 0 | GP0[1] | General Purpose I/O | B | 8 | AJ5 |
| GPIO 0 | GP0[2] | General Purpose I/O | B | 8 | AF7 |
| GPIO 0 | GP0[3] | General Purpose I/O | B | 8 | AH6 |
| GPIO 0 | GP0[4] | General Purpose I/O | B | 8 | AK1 |
| GPIO 0 | GP0[5] | General Purpose I/O | B | 8 | AK2 |
| GPIO 0 | GP0[6] | General Purpose I/O | B | 8 | AG5 |
| GPIO 0 | GP0[7] | General Purpose I/O | B | 8 | AK3 |
| GPIO 1 | GP1[0] | General Purpose I/O | B | 4 | AG6 |
| GPIO 1 | GP1[1] | General Purpose I/O | B | 4 | AK4 |
| GPIO 1 | GP1[2] | General Purpose I/O | B | 4 | AG7 |
| GPIO 1 | GP1[3] | General Purpose I/O | B | 4 | AJ6 |
| GPIO 1 | GP1[4] | General Purpose I/O | B | 4 | AH7 |
| GPIO 1 | GP1[5] | General Purpose I/O | B | 4 | AH8 |
| GPIO 1 | GP1[6] | General Purpose I/O | B | 4 | AL3 |
| GPIO 1 | GP1[7] | General Purpose I/O | B | 4 | AJ7 |
| GPIO 2 | GP2[0] | General Purpose I/O | B | 4 | AM4 |
| GPIO 2 | GP2[1] | General Purpose I/O | B | 4 | AJ8 |
| GPIO 2 | GP2[2] | General Purpose I/O | B | 4 | AL5 |
| GPIO 2 | GP2[3] | General Purpose I/O | B | 4 | AK8 |
| GPIO 2 | GP2[4] | General Purpose I/O | B | 4 | AM5 |
| GPIO 2 | GP2[5] | General Purpose I/O | B | 4 | AH9 |
| GPIO 2 | GP2[6] | General Purpose I/O | B | 4 | AN5 |
| GPIO 2 | GP2[7] | General Purpose I/O | B | 4 | AP5 |
| GPIO 3 | GP3[0] | General Purpose I/O | B | 4 | AK6 |
| GPIO 3 | GP3[1] | General Purpose I/O | B | 4 | AJ9 |
| GPIO 3 | GP3[2] | General Purpose I/O | B | 4 | AL6 |
| GPIO 3 | GP3[3] | General Purpose I/O | B | 4 | AK9 |
| GPIO 3 | GP3[4] | General Purpose I/O | B | 4 | AM6 |
| GPIO 3 | GP3[5] | General Purpose I/O | B | 4 | AH10 |
| GPIO 3 | GP3[6] | General Purpose I/O | B | 4 | AN6 |
| GPIO 3 | GP3[7] | General Purpose I/O | B | 4 | AJ10 |
| JTAG | nBSTAPEN | Boundary Scan TAP Select | IPU | - | C21 |
| JTAG | nTRST | Test Reset | IPU | - | D21 |
| JTAG | RTCK | Sync of Multi-ICE TCK | O | 8 | A21 |
| JTAG | TCK | Test Clock | I | - | A22 |
| JTAG | TDI | Boundary Scan Input | IPU | - | G19 |
| JTAG | TDO | Boundary Scan Output | T | 8 | B21 |
| JTAG | TMS | Test Mode Select | IPU | - | E20 |
| Miscellaneous | BIGENDOUT | Byte Endian Mode or TESTACK | O | 4 | G7 |
| Miscellaneous | CONFIGINIT | Chip configuration | I | - | E8 |
| Miscellaneous | nCONFIGCLR | Chip configuration reset | I | - | E6 |
| Miscellaneous | nPORESET | Power On Reset | I | - | D5 |
| Miscellaneous | nRESET | AMBA AHB Reset | I | - | E7 |
| Miscellaneous | SCANENABLE | Scan Enable | I | - | AJ4 |
| Miscellaneous | TESTSELECT | Manufacturing Test Select | I | - | H6 |
| MPMC | MPMCADDR[0] | Address bus | O | 12 | Y3 |
| MPMC | MPMCADDR[1] | Address bus | O | 12 | Y4 |
| MPMC | MPMCADDR[2] | Address bus | O | 12 | AA5 |
| MPMC | MPMCADDR[3] | Address bus | O | 12 | AA2 |
| MPMC | MPMCADDR[4] | Address bus | O | 12 | AA3 |
| MPMC | MPMCADDR[5] | Address bus | O | 12 | AA4 |
| MPMC | MPMCADDR[6] | Address bus | O | 12 | AA6 |
| MPMC | MPMCADDR[7] | Address bus | O | 12 | AB1 |
| MPMC | MPMCADDR[8] | Address bus | O | 12 | AA7 |
| MPMC | MPMCADDR[9] | Address bus | O | 12 | AB2 |
| MPMC | MPMCADDR[10] | Address bus | O | 12 | AB3 |
| MPMC | MPMCADDR[11] | Address bus | O | 12 | AC1 |
| MPMC | MPMCADDR[12] | Address bus | O | 12 | AB5 |
| MPMC | MPMCADDR[13] | Address bus | O | 12 | AC2 |
| MPMC | MPMCADDR[14] | Address bus | O | 12 | AC3 |
| MPMC | MPMCCKE[0] | Clock enable | O | 8 | U3 |
| MPMC | MPMCCKE[1] | Clock enable | O | 8 | W5 |
| MPMC | MPMCCKE[2] | Clock enable | O | 8 | U2 |
| MPMC | MPMCCKE[3] | Clock enable | O | 8 | W6 |
| MPMC | MPMCCLK[0] | Clock out | O | 16 | R2 |
| MPMC | MPMCCLK[1] | Clock out | O | 16 | R1 |
| MPMC | MPMCCLK[2] | Clock out | O | 16 | T3 |
| MPMC | MPMCCLK[3] | Clock out | O | 16 | T2 |
| MPMC | MPMCCLK[4] | Clock out | O | 16 | T1 |
| MPMC | MPMCDATA[0] | Data bus | B | 8 | AC4 |
| MPMC | MPMCDATA[1] | Data bus | B | 8 | AB6 |
| MPMC | MPMCDATA[2] | Data bus | B | 8 | AD1 |
| MPMC | MPMCDATA[3] | Data bus | B | 8 | AB7 |
| MPMC | MPMCDATA[4] | Data bus | B | 8 | AD2 |
| MPMC | MPMCDATA[5] | Data bus | B | 8 | AD3 |
| MPMC | MPMCDATA[6] | Data bus | B | 8 | AD4 |
| MPMC | MPMCDATA[7] | Data bus | B | 8 | AC5 |
| MPMC | MPMCDATA[8] | Data bus | B | 8 | AE2 |
| MPMC | MPMCDATA[9] | Data bus | B | 8 | AC6 |
| MPMC | MPMCDATA[10] | Data bus | B | 8 | AE3 |
| MPMC | MPMCDATA[11] | Data bus | B | 8 | AF1 |
| MPMC | MPMCDATA[12] | Data bus | B | 8 | AF2 |
| MPMC | MPMCDATA[13] | Data bus | B | 8 | AC7 |
| MPMC | MPMCDATA[14] | Data bus | B | 8 | AF3 |
| MPMC | MPMCDATA[15] | Data bus | B | 8 | AD6 |
| MPMC | MPMCDATA[16] | Data bus | B | 8 | AF4 |
| MPMC | MPMCDATA[17] | Data bus | B | 8 | AG1 |
| MPMC | MPMCDATA[18] | Data bus | B | 8 | AG2 |
| MPMC | MPMCDATA[19] | Data bus | B | 8 | AD5 |
| MPMC | MPMCDATA[20] | Data bus | B | 8 | AG3 |
| MPMC | MPMCDATA[21] | Data bus | B | 8 | AD7 |
| MPMC | MPMCDATA[22] | Data bus | B | 8 | AG4 |
| MPMC | MPMCDATA[23] | Data bus | B | 8 | AH1 |
| MPMC | MPMCDATA[24] | Data bus | B | 8 | AH2 |
| MPMC | MPMCDATA[25] | Data bus | B | 8 | AE5 |
| MPMC | MPMCDATA[26] | Data bus | B | 8 | AH4 |
| MPMC | MPMCDATA[27] | Data bus | B | 8 | AE6 |
| MPMC | MPMCDATA[28] | Data bus | B | 8 | AH5 |
| MPMC | MPMCDATA[29] | Data bus | B | 8 | AJ1 |
| MPMC | MPMCDATA[30] | Data bus | B | 8 | AJ2 |
| MPMC | MPMCDATA[31] | Data bus | B | 8 | AE7 |
| MPMC | MPMCDQM[0] | Data mask & byte lane select | O | 8 | V2 |
| MPMC | MPMCDQM[1] | Data mask & byte lane select | O | 8 | W7 |
| MPMC | MPMCDQM[2] | Data mask & byte lane select | O | 8 | V4 |
| MPMC | MPMCDQM[3] | Data mask & byte lane select | O | 8 | Y5 |
| MPMC | MPMCFBCLK | Clock feedback | I | - | U4 |
| MPMC | MPMCRPVHHOUT | Select Vh level for nRP | O | 4 | AF5 |
| MPMC | nMPMCCAS | Column address strobe | O | 12 | W2 |
| MPMC | nMPMCDYCS[0] | Synch memory chip enable | O | 8 | Y6 |
| MPMC | nMPMCDYCS[1] | Synch memory chip enable | O | 8 | Y1 |
| MPMC | nMPMCDYCS[2] | Synch memory chip enable | O | 8 | Y7 |
| MPMC | nMPMCDYCS[3] | Synch memory chip enable | O | 8 | Y2 |
| MPMC | nMPMCRAS | Row address strobe | O | 12 | W1 |
| MPMC | nMPMCRPOUT | SyncFlash reset power down | O | 4 | AJ3 |
| MPMC | nMPMCWE | Write enable | O | 12 | W3 |
| Power | TAVDD | PLL digital power | PIO | - | C4 |
| Power | TAVSS | PLL digital ground | PIO | - | F7 |
| Power | TVDD1P | PLL analog power | PIO | - | G8 |
| Power | TVSS1P | PLL analog ground | PIO | - | F6 |
| Power | VDDC[0] | Core Power | PC | - | F2 |
| Power | VDDC[1] | Core Power | PC | - | J4 |
| Power | VDDC[2] | Core Power | PC | - | N2 |
| Power | VDDC[3] | Core Power | PC | - | V3 |
| Power | VDDC[4] | Core Power | PC | - | AA1 |
| Power | VDDC[5] | Core Power | PC | - | AE1 |
| Power | VDDC[6] | Core Power | PC | - | AH3 |
| Power | VDDC[7] | Core Power | PC | - | AP6 |
| Power | VDDC[8] | Core Power | PC | - | AP9 |
| Power | VDDC[9] | Core Power | PC | - | AN12 |
| Power | VDDC[10] | Core Power | PC | - | AP20 |
| Power | VDDC[11] | Core Power | PC | - | AP21 |
| Power | VDDC[12] | Core Power | PC | - | AM24 |
| Power | VDDC[13] | Core Power | PC | - | AM27 |
| Power | VDDC[14] | Core Power | PC | - | AJ34 |
| Power | VDDC[15] | Core Power | PC | - | AE32 |
| Power | VDDC[16] | Core Power | PC | - | AA34 |
| Power | VDDC[17] | Core Power | PC | - | V32 |
| Power | VDDC[18] | Core Power | PC | - | R31 |
| Power | VDDC[19] | Core Power | PC | - | K33 |
| Power | VDDC[20] | Core Power | PC | - | G30 |
| Power | VDDC[21] | Core Power | PC | - | A28 |
| Power | VDDC[22] | Core Power | PC | - | D24 |
| Power | VDDC[23] | Core Power | PC | - | C22 |
| Power | VDDC[24] | Core Power | PC | - | B19 |
| Power | VDDC[25] | Core Power | PC | - | C14 |
| Power | VDDC[26] | Core Power | PC | - | A11 |
| Power | VDDC[27] | Core Power | PC | - | C8 |
| Power | VDDIO[0] | I/O Power | PIO | - | B1 |
| Power | VDDIO[1] | I/O Power | PIO | - | D1 |
| Power | VDDIO[2] | I/O Power | PIO | - | V1 |
| Power | VDDIO[3] | I/O Power | PIO | - | AL1 |
| Power | VDDIO[4] | I/O Power | PIO | - | AN1 |
| Power | VDDIO[5] | I/O Power | PIO | - | A2 |
| Power | VDDIO[6] | I/O Power | PIO | - | C2 |
| Power | VDDIO[7] | I/O Power | PIO | - | AM2 |
| Power | VDDIO[8] | I/O Power | PIO | - | AP2 |
| Power | VDDIO[9] | I/O Power | PIO | - | B3 |
| Power | VDDIO[10] | I/O Power | PIO | - | AN3 |
| Power | VDDIO[11] | I/O Power | PIO | - | A4 |
| Power | VDDIO[12] | I/O Power | PIO | - | D4 |
| Power | VDDIO[13] | I/O Power | PIO | - | K4 |
| Power | VDDIO[14] | I/O Power | PIO | - | N4 |
| Power | VDDIO[15] | I/O Power | PIO | - | T4 |
| Power | VDDIO[16] | I/O Power | PIO | - | W4 |
| Power | VDDIO[17] | I/O Power | PIO | - | AB4 |
| Power | VDDIO[18] | I/O Power | PIO | - | AE4 |
| Power | VDDIO[19] | I/O Power | PIO | - | AL4 |
| Power | VDDIO[20] | I/O Power | PIO | - | F5 |
| Power | VDDIO[21] | I/O Power | PIO | - | AK5 |
| Power | VDDIO[22] | I/O Power | PIO | - | D10 |
| Power | VDDIO[23] | I/O Power | PIO | - | AL10 |
| Power | VDDIO[24] | I/O Power | PIO | - | D13 |
| Power | VDDIO[25] | I/O Power | PIO | - | AL13 |
| Power | VDDIO[26] | I/O Power | PIO | - | D16 |
| Power | VDDIO[27] | I/O Power | PIO | - | AL13 |
| Power | VDDIO[28] | I/O Power | PIO | - | D19 |
| Power | VDDIO[29] | I/O Power | PIO | - | AL19 |
| Power | VDDIO[30] | I/O Power | PIO | - | D22 |
| Power | VDDIO[31] | I/O Power | PIO | - | AL22 |
| Power | VDDIO[32] | I/O Power | PIO | - | D25 |
| Power | VDDIO[33] | I/O Power | PIO | - | AL25 |
| Power | VDDIO[34] | I/O Power | PIO | - | E30 |
| Power | VDDIO[35] | I/O Power | PIO | - | AK30 |
| Power | VDDIO[36] | I/O Power | PIO | - | A31 |
| Power | VDDIO[37] | I/O Power | PIO | - | D31 |
| Power | VDDIO[38] | I/O Power | PIO | - | K31 |
| Power | VDDIO[39] | I/O Power | PIO | - | N31 |
| Power | VDDIO[40] | I/O Power | PIO | - | T31 |
| Power | VDDIO[41] | I/O Power | PIO | - | W31 |
| Power | VDDIO[42] | I/O Power | PIO | - | AB31 |
| Power | VDDIO[43] | I/O Power | PIO | - | AE31 |
| Power | VDDIO[44] | I/O Power | PIO | - | AL31 |
| Power | VDDIO[45] | I/O Power | PIO | - | AP31 |
| Power | VDDIO[46] | I/O Power | PIO | - | B32 |
| Power | VDDIO[47] | I/O Power | PIO | - | AN32 |
| Power | VDDIO[48] | I/O Power | PIO | - | A33 |
| Power | VDDIO[49] | I/O Power | PIO | - | C33 |
| Power | VDDIO[50] | I/O Power | PIO | - | AM33 |
| Power | VDDIO[51] | I/O Power | PIO | - | AP33 |
| Power | VDDIO[52] | I/O Power | PIO | - | B34 |
| Power | VDDIO[53] | I/O Power | PIO | - | D34 |
| Power | VDDIO[54] | I/O Power | PIO | - | U34 |
| Power | VDDIO[55] | I/O Power | PIO | - | AL34 |
| Power | VDDIO[56] | I/O Power | PIO | - | AN34 |
| Smart Card | nSCICARDRST | Card reset | O | 4 | R30 |
| Smart Card | nSCICLKEN | Tristate buffer control | O | 4 | P32 |
| Smart Card | nSCIDATAEN | Tristate buffer control | O | 4 | T29 |
| Smart Card | nSCIDATAOUTEN | Serial data buffer control | O | 4 | P33 |
| Smart Card | nSCIVCCEN | Card supply voltage control | O | 4 | P31 |
| Smart Card | SCICLKIN | Clock input from card interface | I | - | R33 |
| Smart Card | SCICLKOUT | Clock output to card interface | T | 4 | P34 |
| Smart Card | SCIDATAIN | Serial data input | I | - | U30 |
| Smart Card | SCIDATAOUTOD | Open drain data output | T | 4 | T30 |
| Smart Card | SCIDETECT | Card detect | I | - | R32 |
| Smart Card | SCIFCB | Function code for type II sync card | O | 4 | N34 |
| Smart Card | SCIREFCLKEXT | External Clock input for SCI | I | - | R34 |
| SSMC | nSMBLS[0] | Byte lane select | O | 8 | AM21 |
| SSMC | nSMBLS[1] | Byte lane select | O | 8 | AJ19 |
| SSMC | nSMBLS[2] | Byte lane select | O | 8 | AL21 |
| SSMC | nSMBLS[3] | Byte lane select | O | 8 | AH19 |
| SSMC | nSMBURSTWAIT | Burst wait mode input | I | - | AL7 |
| SSMC | nSMOEN | Output enable | O | 12 | AP22 |
| SSMC | nSMWEN | Write enable | O | 12 | AP19 |
| SSMC | nSTATICCS[0] | Chip select | O | 8 | AM19 |
| SSMC | nSTATICCS[1] | Chip select | O | 8 | AH18 |
| SSMC | nSTATICCS[2] | Chip select | O | 8 | AN20 |
| SSMC | nSTATICCS[3] | Chip select | O | 8 | AM20 |
| SSMC | nSTATICCS[4] | Chip select | O | 8 | AL20 |
| SSMC | nSTATICCS[5] | Chip select | O | 8 | AJ18 |
| SSMC | nSTATICCS[6] | Chip select | O | 8 | AN21 |
| SSMC | nSTATICCS[7] | Chip select | O | 8 | AK19 |
| SSMC | SMADDR[0] | Address bus | O | 12 | AH15 |
| SSMC | SMADDR[1] | Address bus | O | 12 | AM14 |
| SSMC | SMADDR[2] | Address bus | O | 12 | AJ15 |
| SSMC | SMADDR[3] | Address bus | O | 12 | AN14 |
| SSMC | SMADDR[4] | Address bus | O | 12 | AP14 |
| SSMC | SMADDR[5] | Address bus | O | 12 | AL15 |
| SSMC | SMADDR[6] | Address bus | O | 12 | AH16 |
| SSMC | SMADDR[7] | Address bus | O | 12 | AM15 |
| SSMC | SMADDR[8] | Address bus | O | 12 | AK15 |
| SSMC | SMADDR[9] | Address bus | O | 12 | AN15 |
| SSMC | SMADDR[10] | Address bus | O | 12 | AP15 |
| SSMC | SMADDR[11] | Address bus | O | 12 | AM16 |
| SSMC | SMADDR[12] | Address bus | O | 12 | AJ16 |
| SSMC | SMADDR[13] | Address bus | O | 12 | AN16 |
| SSMC | SMADDR[14] | Address bus | O | 12 | AK17 |
| SSMC | SMADDR[15] | Address bus | O | 12 | AP16 |
| SSMC | SMADDR[16] | Address bus | O | 12 | AL17 |
| SSMC | SMADDR[17] | Address bus | O | 12 | AM17 |
| SSMC | SMADDR[18] | Address bus | O | 12 | AH17 |
| SSMC | SMADDR[19] | Address bus | O | 12 | AN17 |
| SSMC | SMADDR[20] | Address bus | O | 12 | AK16 |
| SSMC | SMADDR[21] | Address bus | O | 12 | AP18 |
| SSMC | SMADDR[22] | Address bus | O | 12 | AN18 |
| SSMC | SMADDR[23] | Address bus | O | 12 | AL18 |
| SSMC | SMADDR[24] | Address bus | O | 12 | AJ17 |
| SSMC | SMADDR[25] | Address bus | O | 12 | AM18 |
| SSMC | SMADDRVALID | Address valid | O | 8 | AK18 |
| SSMC | SMBAA | Burst address advance | O | 8 | AN19 |
| SSMC | SMCANCELWAIT | Wait mode cancel | I | - | AH11 |
| SSMC | SMCLK[0] | Clock out | O | 16 | AM7 |
| SSMC | SMCLK[1] | Clock out | O | 16 | AN7 |
| SSMC | SMCLK[2] | Clock out | O | 16 | AP7 |
| SSMC | SMDATA[0] | Data bus | B | 8 | AK10 |
| SSMC | SMDATA[1] | Data bus | B | 8 | AM8 |
| SSMC | SMDATA[2] | Data bus | B | 8 | AJ11 |
| SSMC | SMDATA[3] | Data bus | B | 8 | AN8 |
| SSMC | SMDATA[4] | Data bus | B | 8 | AK11 |
| SSMC | SMDATA[5] | Data bus | B | 8 | AP8 |
| SSMC | SMDATA[6] | Data bus | B | 8 | AH12 |
| SSMC | SMDATA[7] | Data bus | B | 8 | AL9 |
| SSMC | SMDATA[8] | Data bus | B | 8 | AM9 |
| SSMC | SMDATA[9] | Data bus | B | 8 | AN9 |
| SSMC | SMDATA[10] | Data bus | B | 8 | AJ12 |
| SSMC | SMDATA[11] | Data bus | B | 8 | AM10 |
| SSMC | SMDATA[12] | Data bus | B | 8 | AK12 |
| SSMC | SMDATA[13] | Data bus | B | 8 | AN10 |
| SSMC | SMDATA[14] | Data bus | B | 8 | AH13 |
| SSMC | SMDATA[15] | Data bus | B | 8 | AP10 |
| SSMC | SMDATA[16] | Data bus | B | 8 | AL11 |
| SSMC | SMDATA[17] | Data bus | B | 8 | AM11 |
| SSMC | SMDATA[18] | Data bus | B | 8 | AK13 |
| SSMC | SMDATA[19] | Data bus | B | 8 | AN11 |
| SSMC | SMDATA[20] | Data bus | B | 8 | AJ13 |
| SSMC | SMDATA[21] | Data bus | B | 8 | AP11 |
| SSMC | SMDATA[22] | Data bus | B | 8 | AL12 |
| SSMC | SMDATA[23] | Data bus | B | 8 | AM12 |
| SSMC | SMDATA[24] | Data bus | B | 8 | AH14 |
| SSMC | SMDATA[25] | Data bus | B | 8 | AP12 |
| SSMC | SMDATA[26] | Data bus | B | 8 | AJ14 |
| SSMC | SMDATA[27] | Data bus | B | 8 | AM13 |
| SSMC | SMDATA[28] | Data bus | B | 8 | AK14 |
| SSMC | SMDATA[29] | Data bus | B | 8 | AN13 |
| SSMC | SMDATA[30] | Data bus | B | 8 | AP13 |
| SSMC | SMDATA[31] | Data bus | B | 8 | AL14 |
| SSMC | SMFBCLK | Clock feedback | I | - | AL8 |
| SSMC | SMWAIT | Wait mode input | I | - | AK7 |
| SSP | nSSPCTLOE | Output enable SSPCLKOUT | O | 4 | A20 |
| SSP | nSSPOE | Output enable SSPTXD | O | 4 | E18 |
| SSP | SSPCLKEXT | External Clock input for SSP | I | - | F19 |
| SSP | SSPCLKIN | Clock input | I | - | C20 |
| SSP | SSPCLKOUT | Clock output | O | 4 | G18 |
| SSP | SSPFSSIN | Frame input | I | - | D20 |
| SSP | SSPFSSOUT | Frame or slave select | O | 4 | F18 |
| SSP | SSPRXD | Receive data input | I | - | E19 |
| SSP | SSPTXD | Transmit data output | O | 4 | B20 |
| UART 0 | nSIROUT0 | SIR transmitted serial data | O | 4 | AJ28 |
| UART 0 | nUART0CTS | Clear to send | I | - | AH25 |
| UART 0 | nUART0DCD | Data Carrier detect | I | - | AK28 |
| UART 0 | nUART0DSR | Data Set Ready | I | - | AJ26 |
| UART 0 | nUART0DTR | Data terminal ready | O | 4 | AK26 |
| UART 0 | nUART0Out1 | Out 1 modem status | O | 4 | AK27 |
| UART 0 | nUART0Out2 | Out 2 modem status | O | 4 | AL30 |
| UART 0 | nUART0RI | Ring Indicator | I | - | AP30 |
| UART 0 | nUART0RTS | Request to send | O | 4 | AK29 |
| UART 0 | SIRIN0 | SIR received serial data | I | - | AN30 |
| UART 0 | UART0RXD | Received serial data | I | - | AH26 |
| UART 0 | UART0TXD | Transmitted serial data | O | 4 | AM30 |
| UART 0 | UARTCLKEXT | External Clock input for UART | I | - | AL29 |
| UART 1 | nUART1CTS | Clear to send | I | - | AM31 |
| UART 1 | nUART1RTS | Request to send | O | 4 | AG28 |
| UART 1 | UART1RXD | Received serial data | I | - | AJ27 |
| UART 1 | UART1TXD | Transmitted serial data | O | 4 | AH27 |
| UART 2 | nUART2CTS | Clear to send | I | - | AH29 |
| UART 2 | nUART2RTS | Request to send | O | 4 | AH30 |
| UART 2 | UART2RXD | Received serial data | I | - | AJ29 |
| UART 2 | UART2TXD | Transmitted serial data | O | 4 | AH28 |
| VIC | PWRFAIL | Interrupt source | I | - | AL27 |
| VIC | VICINTSOURCE[21] | Interrupt source | I | - | AJ24 |
| VIC | VICINTSOURCE[22] | Interrupt source | I | - | AP28 |
| VIC | VICINTSOURCE[23] | Interrupt source | I | - | AN28 |
| VIC | VICINTSOURCE[24] | Interrupt source | I | - | AM28 |
| VIC | VICINTSOURCE[25] | Interrupt source | I | - | AH24 |
| VIC | VICINTSOURCE[26] | Interrupt source | I | - | AL28 |
| VIC | VICINTSOURCE[27] | Interrupt source | I | - | AJ25 |
| VIC | VICINTSOURCE[28] | Interrupt source | I | - | AP29 |
| VIC | VICINTSOURCE[29] | Interrupt source | I | - | AK25 |
| VIC | VICINTSOURCE[30] | Interrupt source | I | - | AN29 |
| VIC | VICINTSOURCE[31] | Interrupt source | I | - | AM29 |
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