15.2. Functional description

This section gives a basic overview of the Dual-Timer module operation.

The Dual-Timer module consists of two identical programmable Free Running Counters (FRCs) that can be configured for 32-bit or 16-bit operation and one of three timer modes;

The FRCs operate from a common timer clock, a buffered version of HCLK with each FRC having its own clock enable input, TIMCLKEN1 and TIMCLKEN2. Each FRC also has a prescaler that can divide down the enabled timer clock rate by 1, 16, or 256. This enables the count rate for each FRC to be controlled independently using their individual clock enables and prescalers.

The operation of each Timer module is identical. A Timer module can be programmed for a 32-bit or 16-bit counter size and one of three timer modes using the Control Register. The three timer modes are:


The counter operates continuously and wraps around to its maximum value each time that it reaches zero.


The counter operates continuously by reloading from the Load Register each time that the counter reaches zero.


The counter is loaded with a new value by writing to the Load Register. The counter decrements to zero and then halts until it is reprogrammed.

The timer count is loaded by writing to the Load Register and, if enabled, the timer count decrements at a rate determined by the timer clock, TIMCLKENx, and the prescaler setting. When the Timer counter is already running, writing to the Load Register causes the counter to immediately restart from the new value.

An alternative way of loading the Timer count is by writing to the Background Load Register. This has no immediate effect on the current count but the counter continues to decrement. On reaching zero, the Timer count is reloaded from the new load value if it is in periodic mode.

When the Timer count reaches zero an interrupt is generated. The interrupt is cleared by writing to the Interrupt Clear Register. The external interrupt signals can be masked off by the Interrupt Mask Registers.

The current counter value can be read from the Value Register at any time.

Figure 15.1 shows a simplified block diagram of the module. At reset, the timers are clocked by an external reference on the REFCLK32K input. You can use the system controller to change the timer reference to the TIMCLKEXT input signal (see Clock control).


In Figure 15.1, test logic is not shown for clarity.

Figure 15.1. Simplified block diagram

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