4.2.1. Bus Cycle Analyzer

The Bus Cycle Analyzer (BCA) provides information about bus activity on a cycle by cycle basis. A packet of information is created on every bus clock. Access to the real-time status of the layers is made available through a set of pins on the chip named AHBMONITOR. Use the AHBMONITOR connections to monitor the activity of the AHB interconnects through a logic analyzer.

The AHBMONITOR port

The AHBMONITOR port consists of 33 data output pins that export status data packets at the AHB clock rate. A localized clock is exported on AHBMONITOR[33].

To produce minimal loading effects on the respective bus layers and to improve setup and hold characteristics, the logic in the BCA includes registers to de-pipeline that part of the information that it captured from the address phase. The registering of these signals causes the status reported at the port to be three HCLK cycles behind the actual activity on the interconnect.

AHB Monitor packet format

There are 33 bits per data packet. To simplify the subsequent analysis of the data, there are completely separate groups of bits associated with each AHB layer and the GXI. The packet can be viewed as seven independent subpackets as shown in Figure 4.2. There are six bits assigned to the ARM-D layer, five to each of the DMA and Expansion layers, and four for the LCD, ARM-I and GXI layers.

Figure 4.2. AHB Monitor packet format

AHB Layer Cycle States

The states that can be reported for an AHB layer are shown in Table 4.1.

Table 4.1. Cycle states

SymbolNameDescription
IIdleThe bus master is performing, and hence completing, an IDLE transfer.
BBusyThe bus master is performing, and hence completing, a BUSY transfer.
ENError_NextThe bus master is receiving the first half of an ERROR response.
RNRetry_NextThe bus master is receiving the first half of a RETRY response.
WSWait_SlaveThe bus master is incurring a wait state as a result of the slave.
WBWait_BusThe bus master is incurring a wait state as a result of the matrix latency on a new connection.
WAWait_ArbiterThe bus master is incurring a wait state as a result of the arbitration latency of competing masters.
SbSequential_Burst_Type_bThe bus master is completing a data transfer sequential to the last one. Set of states representing each possible burst type.
NRsNewReadSlave_sThe bus master is completing a Nonsequential Read from slave number <s>
NWsNewWriteSlave_sThe bus master is completing a Nonsequential Write to slave number <s>

The total number of different NRs and NWs states, that are valid, is dependent upon the layer - some masters only perform reads and most have connections to only a subset of the possible slaves. Similarly the number of valid Sb states is dependent upon the layer because most masters are not capable of producing all possible burst types. For these reasons, the format of the encoded signals has been developed to allow the bit allocation per layer as stated in the previous section.

Assigning different states for Sequential and Nonsequential transfers means that it is possible to reconstruct burst information from the data stream. It is not necessary to identify either the transfer direction or the slave number in a sequential transfer because the bus protocol defines that both of these must remain constant throughout a burst, so is the same as the most recent NRs or NWs state. Similarly, it is not necessary to identify the burst type in a nonsequential transfer because this is indicated in any subsequent sequential transfers.

The Error_Next and Retry_Next responses are indicated during the first cycle of the two cycle response sequence, which allows the progress of the burst in second cycle as can occur with an error response.

Table 4.2 shows an example pattern of transfers and the data stream produced.

Table 4.2. Sample output

Pattern on busDescription
IIdle Transfer
WBFirst write transfer to slave 1 incurring one wait state imposed by the bus matrix
NW1-
S_INCR4Second write transfer to slave 1 in an incrementing burst of four
S_INCR4Third write transfer to slave 1 in an incrementing burst of four
S_INCR4Fourth write transfer to slave 1 in an incrementing burst of four
WBFirst read transfer from slave 2, one wait states from the bus connect latency and one from the arbitration latency
WA-
NR2-
WSSecond read transfer from slave 2 in a wrapping burst of 4, one wait state inserted by the slave
S_WRAP4-
WSThird read transfer from slave 2 in a wrapping burst of 4, one wait state inserted by the slave
S_WRAP4-
WSFourth read transfer from slave 2 in a wrapping burst of 4, one wait state inserted by the slave
S_WRAP4 -

AHB Cycle State encoding

Table 4.3 shows the bit pattern encoding used for each of the possible Bus Cycle States on each layer and shows which of those values can actually be generated by that layer (boxes marked with a Y).

Note

The LCD and ARM-I layers can only generate bit patterns with bits [5] and [4] are held at 0. Similarly, the EXPansion, DMA0, and DMA0 layers can only generate bit patterns with bit [5] of the Code field at 0. There are six bits assigned to the ARM-D layer, five to each of the DMA and Expansion layers, and four for the LCD, ARM-I and GXI layers.

Table 4.3. Bus state bit patterns

Symbol and bus state[5][1][4][2][3:0] ARM-D [28:23]ARM-I [22:19]DMA-0 [18:14]DMA-1 [13:9]EXP [8:4]LCD [3:0]
I, Idle000000YYYYYY
S_INCR, Sequential_INCR000001--YYYY
B, Busy000010----YY
S_INCR4, Sequential_INCR4000011YYYYYY
S_WRAP8, Sequential_WRAP8000100YY--Y-
S_INCR8, Sequential_INCR8000101Y-YYYY
EN, Error Next000110YYYYYY
S_INCR16, Sequential_INCR16000111--YYYY
NR_EXP1, Expansion Bridge 1001000YYYYYY
NR_EXP2, Expansion Bridge 2001001YYYYYY
NR_MPMC, MPMC001010YY-YYY
NR_SMC, SMC001011YY-YYY
WS, Wait_Slave001100YYYYYY
WB, Wait_Bus001101YYYYYY
WA, Wait_Arbiter001110YYYYYY
HRESET001111-Y---Y
NW_EXP1, Expansion Bridge 1010000Y-YYY-
NW_EXP2, Expansion Bridge 2010001Y-YYY-
NW_MPMC, MPMC010010Y--YY-
NW_SMC, SMC010011Y--YY-
NW_APBDMA, APB bridge to DMA peripherals010100Y--YY-
NW_APBCore, APB bridge to Core peripherals010101Y-Y-Y-
NW_AHBMON, AHB Monitor registers010110Y---Y-
0x17, Unused010111------
0x18 - 0x19, Unused01100x------
S_WRAP4, Sequential_WRAP4011010----Y-
S_WRAP16, Sequential_WRAP16011011----Y-
NR_APBDMA, APB bridge to DMA peripherals011100Y-Y-Y-
NR_APBCore, APB bridge to Core peripherals011101Y---Y-
NR_AHBMON, AHB Monitor registers011110Y---Y-
HRESET011111--YYY-
0x20- 0x2F, Unused10xxxx------
NW_SMCCFG, SMC110111Y-----
NW_MPMCCFG, MPMC config registers110000Y-----
NW_VIC, VIC registers110010Y-----
NW_CLCDC, CLCDC registers110011Y-----
NW_DMAC, DMAC registers110100Y-----
NW_MBX, MBX registers110101Y-----
0x36 - 0x37, Unused11011x------
NR_SMCCFG, Read SMC configuration111000Y-----
NR_MPMCCFG, Read MPMC configuration 111001Y-----
NR_VIC, Read from VIC111010Y-----
NR_CLCDC, Read from CLCDC 111011Y-----
NR_DMAC, DMAC registers111100Y-----
NR_MBX, MBX registers111101Y-----
RN, Retry_Next111110Y-----
HRESET, Bus reset111111------

[1] The ARM-D bus state code is 6-bits long.

[2] The DMA-0, DMA-1, and EXP bus state codes are 5-bits long.

GXI Cycle States and Encoding

The GXI can perform concurrent read and write activities due to the split transfer architecture it employs. Therefore, the four debug output pins related to the GXI are divided into two, providing separate state information for the read and write channels. The four bits dedicated to the GXI assign the upper two bits to the read channel and the lower bits to the write channel, AHBMONITOR[32:29] = {ReadState, WriteState}.

Note

The GXI debug is a registered output based on the registered forms of the GXI bus similar to the approach taken for the AHB layers, therefore the reported activity is similarly delayed.

The two GXI channels behave differently and have different encoding presented in Table 4.4 and Table 4.5. Table 4.4 shows the states of the read data channel and Table 4.5 shows the states of the address channel.

Table 4.4. Bit patterns for GXI states for read channel

SymbolNameEncoding [32:31]Description
IIdle00The GXI read data channel is idle, that is, no transfers are active nor pending
WPWait Pending01The GXI read data channel has been stalled and has one or more transfers waiting for completion
TnPTransfer and None Pending10The GXI read data channel is taking part in a transfer without any further transfers wait for completion
TPTransfer and Pending11The GXI read data channel is taking part in a transfer with one or more additional transfers waiting for completion

Table 4.5. Bit patterns for GXI state for address channel

SymbolNameEncoding [30:29]Description
IIdle00The GXI address channel is idle, that is, no transfers are active nor pending
WWait01The GXI address channel is waiting on a read or write address transfer
RdRead10The GXI address channel is completing a read address transfer
WrWrite11The GXI address channel is completing a write transfer
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