2.1.6. Watchdog and Timer module clock enable generation

Enable signals are generated to enable the Timer and Watchdog modules to be clocked at a rate that is independent of the system clock. The enable signals are generated by sampling a free-running, constant frequency clock from the TIMCLKEXT input and generating an active HIGH pulse for a single SCLK clock cycle on each rising edge of the input clock. This is shown in Figure 2.1.

Figure 2.1. Enable signal generation for the Timer and Watchdog modules

The module enable signals are:

The enable signal for the Watchdog module is generated from the REFCLK input.

The Timer module enable signals are selectively generated as defined in the System Control Register from either:

Additionally, to enable the Watchdog and Timer modules to be clocked directly at the system clock rate, it is also possible to selectively force the enable outputs HIGH.

The watchdog clock enable output can be forced inactive by deasserting the WDEN input. For example, the WDEN input can be used to disable the watchdog timer when the processor core is in a debug state.

Watchdog and Timer modules clock enable generation

The Watchdog and Timer modules have clock enable terms generated synchronously to CLK by the System Controller:






To enable the Timer and Watchdog module enable signals to be generated at a constant rate independently of the system clock, the signals are derived from asynchronous, fixed-rate clock inputs.

The Watchdog module enable is generated from the REFCLK input and a single WDOGCLKEN pulse is generated on every rising edge of REFCLK.

The Timer module enable can be selectively generated from either the REFCLK or TIMCLK inputs. This is shown for WDOGCLKEN and TIMER1CLKEN in Figure 2.2.

Figure 2.2. Reference frequency select for Watchdog and Timer modules clock enable

To support debugging the system software, both Timer and Watchdog modules stall when the ARM processor is in Debug mode.

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