2.2.3. Peripheral clock selection

The external clock signals are user-defined off-chip clocks. They are gated by the System Controller outputs PERIPHCLKENx. Alternatively, the peripheral clocks may be derived from HCLK.

In normal operation the System Controller output PERIPHCTRL0x selects the clock source. To ensure correct operation of the peripheral PERIPHCTRL0x should not change state while the gate is enabled. At reset the PERIPHCTRL0x outputs are set low by the system controller, therefore selecting the External Clocks.

Table 2.2. External peripheral clocks and clock control signals

External ClockPeripheral ClockPERIPHCLKENx and PERIPHCLKSTATxPERIPHCTRL0x
CLCDCLKEXTINCLCDCLK33
SSPCLKEXTINSSPCLK44
SCIREFCLKEXTINSCIREFCLK55
UARTCLKEXTINUARTCLK066
UARTCLKEXTINUARTCLK177
UARTCLKEXTINUARTCLK288
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