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The allocation of the DMAC peripheral request lines is defined in Table 8.1.
Table 8.1. DMA channel allocation
| DMA requester | DMA channel |
|---|---|
| UART0 Tx | 15 |
| UART0 Rx | 14 |
| UART1 Tx | 13 |
| UART1 Rx | 12 |
| UART2 Tx | 11 |
| UART2 Rx | 10 |
| SSP Tx | 9 |
| SSP Rx | 8 |
| SCI Tx | 7 |
| SCI Rx | 6 |
| External DMA request [5:0] | 5:0 |
The master interfaces of the DMAC both drive single master AHBs. Therefore:
the HGRANT inputs are tied HIGH
the HBUSREQ outputs are left unconnected.
The only interrupt from the DMAC that is connected to the VIC is the combined interrupt source DMACINTR. The remaining interrupt sources, DMAINTERR and DMAITTC, are left unconnected.
| Copyright © 2004, 2006 ARM Limited. All rights reserved. | ARM DDI 0287B |
| Non-Confidential | |
| PDF version | |
| Home > Controllers and Peripherals > Direct Memory Access Controller (DMAC) > Functional description > Peripheral integration |