8.2.1. Peripheral integration

The allocation of the DMAC peripheral request lines is defined in Table 8.1.

Table 8.1. DMA channel allocation

DMA requesterDMA channel
UART0 Tx15
UART0 Rx14
UART1 Tx13
UART1 Rx12
UART2 Tx11
UART2 Rx10
SSP Tx9
SSP Rx8
SCI Tx7
SCI Rx6
External DMA request [5:0]5:0

The master interfaces of the DMAC both drive single master AHBs. Therefore:

The only interrupt from the DMAC that is connected to the VIC is the combined interrupt source DMACINTR. The remaining interrupt sources, DMAINTERR and DMAITTC, are left unconnected.

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