5.3.2. Hardware cursor registers

Table 5.11 lists the hardware cursor registers.

Table 5.11. PrimeCell CLCDC register summary

NameAddress

Type

Reset value

Description

CursorImage0x10120800-0x10120BFC

R/W

0x00000000

See Cursor Image RAM Register
ClcdCrsrCtrl

0x10120C00

R/W

0x00

See Cursor Control Register

ClcdCrsrConfig

0x10120C04

R/W

0x0

See Cursor Configuration Register

ClcdCrsrPalette0

0x10120C08

R/W

0x000000

See Cursor Palette Registers

ClcdCrsrPalette1

0x10120C0C

R/W

0x000000

See Cursor Palette Registers

ClcdCrsrXY

0x10120C10

R/W

0x00000000

See Cursor XY Position Register

ClcdCrsrClip

0x10120C14

R/W

0x0000

See Cursor Clip Position Register

-

0x10120C18-0x10120C1C

--Reserved
ClcdCrsrIMSC

0x10120C20

R/W

0x0

See Cursor Interrupt Mask Set/Clear Register

ClcdCrsrICR

0x10120C24

WO0x0

See Cursor Interrupt Clear Register

ClcdCrsrRIS

0x10120C28

RO0x0

See Cursor Raw Interrupt Status Register

ClcdCrsrMIS

0x10120C2C

RO0x0

See Cursor Masked Interrupt Status Register

-

0x10120C30-0x10120FDC

--Reserved
CLCDPeriphID0

0x10120FE0

RO

0x11

See Peripheral Identification Registers

CLCDPeriphID1

0x10120FE4

RO

0x11

See Peripheral Identification Registers

CLCDPeriphID2

0x10120FE8

RO

0x04

See Peripheral Identification Registers

CLCDPeriphID3

0x10120FEC

RO

0x00

See Peripheral Identification Registers

CLCDPCellID0

0x10120FF0

RO

0x0D

See PrimeCell Identification Registers

CLCDPCellID1

0x10120FF4

RO

0xF0

See PrimeCell Identification Registers

CLCDPCellID2

0x10120FF8

RO

0x05

See PrimeCell Identification Registers

CLCDPCellID3

0x10120FFC

RO

0xB1

See PrimeCell Identification Registers

Cursor Image RAM Register

The CursorImage Register is read and write. It contains 256-word wide values which are used to define the image or images overlaid by the hardware cursor mechanism. The image must always be stored in LBBP mode (little-endian byte, big-endian pixel) mode, as described in Image format. Two bits are used to encode color and transparency for each pixel in the cursor.

Depending on the state of bit 0 in the ClcdCrsrConfig Register (see Cursor Configuration Register), the cursor image RAM contains either four 32x32 cursor images, or a single 64x64 cursor.

The two colors defined for the cursor are mapped onto values from the ClcdCrsrPalette0 and ClcdCrsrPalette1 Registers (see Cursor Palette Registers).

Cursor Control Register

The ClcdCrsrCtrl Register is read and write. It provides access to frequently used cursor functions, such as display on/off control for the cursor, and the cursor number for 32x32 bit cursors.

Figure 5.7 shows the register bit assignments.

Figure 5.7. ClcdCrsrCtrl Register bit assignments

Table 5.12 lists the register bit assignments.

Table 5.12. ClcdCrsrCtrl Register bit assignments

BitNameFunction
[31:6]-

Reserved, read undefined, do not modify.

[5:4]CrsrNumber[1:0]

Cursor Image number.

This field provides an offset into the cursor image buffer, to enable one of four 32x32 cursors to be addressed. The images each occupy one quarter of the image memory, with Cursor0 from location 0, followed by Cursor1 from address 0x100, Cursor2 from 0x200 and Cursor3 from 0x300.

If the cursor size is 64x64 this field has no effect because there is only space for one cursor of this size in the image buffer.

If the cursor size is 32x32:

11 = Cursor3

10 = Cursor2

01 = Cursor1

00 = Cursor0.

Frame Synchronization:

Similar synchronization rules apply to the cursor number as apply to the cursor coordinates:

  • if CrsrFramesync is 1, the displayed cursor image is only changed during the vertical frame blanking period.

  • if CrsrFrameSync is 0, the cursor image index is changed immediately, even if the cursor is currently being scanned.

[3:1]-

Reserved, read undefined, do not modify.

[0]CrsrOn1 = Cursor is displayed.0 = Cursor not displayed.

Cursor Configuration Register

The ClcdCrsrConfig Register is read and write. It provides overall configuration information for the hardware cursor.

Figure 5.8 shows the register bit assignments.

Figure 5.8. ClcdCrsrConfig Register bit assignments

Table 5.13 lists the register bit assignments.

Table 5.13. ClcdCrsrConfig Register bit assignments

BitNameFunction
[31:2]-

Reserved, read undefined, do not modify

[1]CrsrFrameSync0 = Cursor coordinates asynchronous1 = Cursor coordinates synchronized to frame synchronization pulse
[0]CrsrSize0 = 32x32 pixel cursor1 = 64x64 pixel cursor

Cursor Palette Registers

The ClcdCrsrPalette0 and ClcdCrsrPalette1 Registers are read and write. They provide color palette information for the visible colors of the cursor:

  • Colour0 is mapped through CrsrPalette0

  • Colour1 is mapped through CrsrPalette1.

The registers provide 24-bit RGB values that are displayed according to the abilities of the LCD panel in the same way as the frame-buffers palette output is displayed.

In mono STN, only Red[7:4] are significant and, in STN color Red[7:4], Blue[7:4] and Green[7:4] are significant. In 24 bits per pixel, all 24 bits of the palette registers are significant.

Figure 5.9 shows the register bit assignments.

Figure 5.9. ClcdCrsrPalette0 and ClcdCrsrPalette1 Register bit assignments

Table 5.14 lists the register bit assignments.

Table 5.14. ClcdCrsrPalette0 and ClcdCrsrPalette1 Register bit assignments

BitNameFunction
[31:24]-

Reserved, read undefined, do not modify

[23:16]BlueBlue color component
[15:8]GreenGreen color component
[7:0]RedRed color component

Cursor XY Position Register

The ClcdCrsrXY Register is read and write. It defines the distance of the top-left edge of the cursor from the top-left side of the cursor overlay.

Figure 5.10 shows the register bit assignments.

Figure 5.10. ClcdCrsrXY Register bit assignments

Table 5.15 lists the register bit assignments.

Table 5.15. ClcdCrsrXY Register bit assignments

BitNameFunction
[31:28]-

Reserved, read undefined, do not modify.

[27:26]CrsrY (expansion)Reserved for coordinate expansion. Must be written as zero.
[25:16]CrsrY

Y ordinate of the cursor origin measured in pixels.

When 0, the top edge of the cursor is at the top of the display.

[15:12]-

Reserved, read undefined, do not modify.

[11:10]

CrsrX (expansion)

Reserved for coordinate expansion. Must be written as zero.

[9:0]

CrsrX

X ordinate of the cursor origin measured in pixels.

When 0, the left edge of the cursor is at the left edge of the display.

If CrsrFrameSync is 0, the cursor position changes immediately, even if the cursor is currently being scanned.

If CrsrFramesync is 1, the cursor position is only changed during the next vertical frame blanking period.

Cursor Clip Position Register

The ClcdCrsrClip Register is read and write. It defines the distance from the top-left edge of the cursor image, to the first displayed pixel in the cursor image.

Figure 5.11 shows the register bit assignments.

Figure 5.11. ClcdCrsrClip Register bit assignments

Table 5.16 lists the register bit assignments.

Table 5.16. ClcdCrsrClip Register bit assignments

BitNameFunction
[31:14]

-

Reserved, read undefined, do not modify.

[13:8]

CrsrClipY

Distance from top of cursor image to the first displayed pixel in cursor.

When 0, the first displayed pixel is from the top line of the cursor image.

[7:6]

-

Reserved, read undefined, do not modify.

[5:0]

CrsrClipX

Distance from left edge of cursor image to the first displayed pixel of cursor.

When 0, the first pixel of the cursor line is displayed.

Different synchronization rules apply to the Cursor Clip Registers than apply to the cursor coordinates.

If CrsrFrameSync is 0, the cursor clip point is changed immediately, even if the cursor is currently being scanned.

If CrsrFramesync is 1, the displayed cursor image is only changed during the vertical frame blanking period, providing that the cursor position has been updated since the Clip Register was programmed. Therefore, when programming, the Clip Register must be written before the Position Register (ClcdCrsrXY) to ensure that in a given frame, the clip and position information is coherent.

Cursor Interrupt Mask Set/Clear Register

The ClcdCrsrIMSC Register is read and write. It is used to enable the cursor interrupt to the processor.

Figure 5.12 shows the register bit assignments.

Figure 5.12. ClcdCrsrIMSC Register bit assignments

Table 5.17 lists the register bit assignments.

Table 5.17. ClcdCrsrIMSC Register bit assignments

Bit

Name

Function

[31:1]

-

Reserved, read undefined, do not modify.

[0]

CrsrIM

When set, the cursor interrupts the processor immediately after reading of the last word of cursor image.

When clear, the cursor never interrupts the processor.

Cursor Interrupt Clear Register

The ClcdCrsrICR Register is write-only. It is used by software to clear the cursor interrupt status and the cursor interrupt signal to the processor.

Figure 5.13 shows the register bit assignments.

Figure 5.13. ClcdCrsrICR Register bit assignments

Table 5.18 lists the register bit assignments.

Table 5.18. ClcdCrsrICR Register bit assignments

Bit

Name

Function

[31:1]

-

Reserved, do not modify.

[0]

CrsrIC

When set the cursor interrupt status is cleared.Writing 0 to this bit has no effect.

Cursor Raw Interrupt Status Register

The ClcdCrsrRIS Register is read-only. It is set to indicate a cursor interrupt, and, when enabled, controls the state of the interrupt signal to the system interrupt controller.

Note

The ClcdCrsrRIS Register is valid regardless of the state of the CrsrIMSC bit.

Figure 5.14 shows the register bit assignments.

Figure 5.14. ClcdCrsrRIS Register bit assignments

Table 5.19 lists the register bit assignments.

Table 5.19. ClcdCrsrRIS Register bit assignments

Bit

Name

Function

[31:1]

-

Reserved, read undefined.

[0]

CrsrRIS

The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame.

This bit is cleared by writing to the CrsrIC bit in the ClcdCrsrICR Register. See Cursor Interrupt Clear Register.

Cursor Masked Interrupt Status Register

The ClcdCrsrMIS Register is read-only. It is set to indicate a cursor interrupt providing that the interrupt bit is not masked.

Figure 5.15 shows the register bit assignments.

Figure 5.15. ClcdCrsrMIS Register bit assignments

Table 5.20 lists the register bit assignments.

Table 5.20. ClcdCrsrMIS Register bit assignments

Bit

Name

Function

[31:1]

-

Reserved, read undefined.

[0]

CrsrMIS

The cursor interrupt status is set immediately after the last data read from the cursor image for the current frame, providing that the corresponding bit in the ClcdCrsrIMSC Register is set.

The bit remains clear if the ClcdCrsrIMSC Register is clear.

This bit is cleared by writing to the ClcdCrsrICR Register. See Cursor Interrupt Clear Register.

Peripheral Identification Registers

The CLCDPeriphID0-3 Registers are four 8-bit read-only registers that span address locations 0xFE0-0xFEC. The registers can conceptually be treated as a single 32-bit register. The registers provide the peripheral options listed in Table 5.21.

Table 5.21. Peripheral Identification Register options

Bit

Function

PartNumber[11:0]

Identifies the peripheral. The three-digit product code 0x11 is used.

DesignerID[19:12]

Identifies the designer. ARM Limited is 0x41, ASCII A.

Revision[23:20]

Identifies the revision number of the peripheral. The revision number starts from 0 and is revision dependent.

Configuration[31:24]

Identifies the configuration option of the peripheral. The configuration value is 0.

Figure 5.16 shows the register bit assignments.

Figure 5.16. CLCDPeriphID0-3 Register bit assignments

The CLCDPeriphID0 Register is read-only. It is hard-coded and the fields in the register determine the reset value. Table 5.22 lists the register bit assignments.

Table 5.22. CLCDPeriphID0 Register bit assignments

Bit

Name

Function

[31:8]

Reserved

Reserved, read undefined

[7:0]

PartNumber0

These bits read back as 0x11

The CLCDPeriphID1 Register is read-only. It is hard-coded and the fields in the register determine the reset value. Table 5.23 lists the register bit assignments.

Table 5.23. CLCDPeriphID1 Register bit assignments

Bit

Name

Function

[31:8]

Reserved

Reserved, read undefined

[7:4]

Designer0

These bits read back as 0x1

[3:0]

PartNumber1

These bits read back as 0x1

The CLCDPeriphID2 Register is read-only. It is hard-coded and the fields in the register determine the reset value. Table 5.24 lists the register bit assignments.

Table 5.24. CLCDPeriphID2 Register bit assignments

Bit

Name

Function

[31:8]

Reserved

Reserved, read undefined

[7:4]

Revision

These bits read back as 0x0

[3:0]

Designer1

These bits read back as 0x4

The CLCDPeriphID3 Register is read-only. It is hard-coded and the fields in the register determine the reset value. Table 5.25 lists the register bit assignments.

Table 5.25. CLCDPeriphID3 Register bit assignments

Bit

Name

Function

[31:8]

Reserved

Reserved, read undefined

[7:0]

Configuration

These bits read back as 0x0

PrimeCell Identification Registers

The CLCDPCellID0-3 Registers are four 8-bit read-only registers that span address locations 0xFF0-0xFFC. The registers can conceptually be treated as a single 32-bit register. The register is used as a standard cross-peripheral identification system. Figure 5.17 shows the register bit assignments.

Figure 5.17. CLCDCPCellID0-3 Register bit assignments

The CLCDPCellID0 Register is read-only. It is hard-coded and the fields in the register determine the reset value. Table 5.26 lists the register bit assignments.

Table 5.26. CLCDPCellID0 Register bit assignments

Bit

Name

Function

[31:8]

Reserved

Reserved, read undefined

[7:0]

CLCDPCellID0

These bits read back as 0x0D

The CLCDPCellID1 Register is read-only. It is hard-coded and the fields in the register determine the reset value. Table 5.27 lists the register bit assignments.

Table 5.27. CLCDPCellID1 Register bit assignments

Bit

Name

Function

[31:8]

Reserved

Reserved, read undefined

[7:0]

CLCDPCellID1

These bits read back as 0xF0

The CLCDPCellID2 Register is read-only. It is hard-coded and the fields in the register determine the reset value. Table 5.28 lists the register bit assignments.

Table 5.28. CLCDPCellID2 Register bit assignments

Bit

Name

Function

[31:8]

Reserved

Reserved, read undefined

[7:0]

CLCDPCellID2

These bits read back as 0x05

The CLCDPCellID3 Register is read-only. It is hard-coded and the fields in the register determine the reset value. Table 5.29 lists the register bit assignments.

Table 5.29. CLCDPCellID3 Register bit assignments

Bit

Name

Function

[31:8]

Reserved

Reserved, read undefined

[7:0]

CLCDPCellID3

These bits read back as 0xB1

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