2.3. External configuration signals

The configuration block is used to define the operating mode of the chip. It samples the state of HDATAM2[28:0] pads while the rest of the chip is held in reset. The state of these pads can then be held to drive configuration signals within the chip. The operating mode of the chip is then defined when reset is released.

Note

In a typical device, the configuration signals would be tied HIGH or LOW. The configuration signals are brought out of the chip to allow different system settings to be tested with the ARM926PXP development chip.

The configuration block reset nCONFIGRST and clock CONFIGINIT are independent of the rest of the chip. While the chip is held in reset the configuration block can be reset and sample the input data CONFIGDATA[28:0] to set the mode of the chip. The chip can then be released from reset and operate in the defined mode. The reset state of the configuration signals defines a default mode that can be used instead of sampling pads on reset.

See Table 2.3 for the source of the configuration signals and Table 2.4 for the destination of the configuration signals.

Table 2.3. Configuration signal sources

Signal nameSourceDescription
CONFIGDATA[28:0]HDATAM2[28:0]Configuration signals from data bus pads.
nCONFIGCLRClock and reset controllerForce all configuration signals to reset state (active LOW).
CONFIGINITClock and reset controllerSample status of pads on rising edge.

Table 2.4. Configuration signal destinations

Signal nameDestinationDescription
CFGCPUVINITHIARM926EJ-S processor VINITHI

Determines the reset location of the exception vectors for the ARM926EJ-S processor.When LOW, the vectors are located at 0x0000000. When HIGH, the vectors are located at 0xFFFF0000.

The reset value is 0. The value is loaded from HDATAM2[0] during reconfiguration.

CFGCPUBIGENDINARM926EJ-S processor BIGENDINIT

Defines the byte endian mode at reset. When LOW, little endianness is used. When HIGH, big endianness is used.

The reset value is 0. The value is loaded from HDATAM2[1] during reconfiguration.

CFGVFPENABLEClock and reset controller and coprocessor multiplexor.

VFP9-S coprocessor enable (active HIGH).

The reset value is 1. The value is loaded from HDATAM2[2] during reconfiguration.

CFGMPMCnSMCARM926PXP development chip AMBA infrastructure MPMCnSMC

Defines which static memory controller is used. When LOW, the SMC is used. When HIGH, the MPMC is used.

The reset value is 0. The value is loaded from HDATAM2[3] during reconfiguration.

CFGREMAPSTEXENARM926PXP development chip AMBA infrastructure.

Static memory and expansion memory alias enable. When HIGH and CFGREMAPDYEXEN is LOW, then static memory is aliased to 0x00000000. When HIGH and CFGREMAPDYEXEN is HIGH, then expansion memory is aliased to 0x00000000.

The reset value is 1. The value is loaded from HDATAM2[4] during reconfiguration.

CFGREMAPDYEXENARM926PXP development chip AMBA infrastructure

Dynamic memory and expansion memory alias enable. When HIGH and CFGREMAPSTEXEN is HIGH, then expansion memory is aliased to 0x00000000.

Note

The combination of CFGREMAPDYEXEN HIGH and CFGREMAPSTEXEN LOW is reserved and must not be used.

The reset value is 0. A new value is loaded from HDATAM2[5] during reconfiguration.

CFGBRIDGEMEMMAPARM926PXP development chip AMBA infrastructure

Select memory map for the off-chip bridges.

The reset value is 1. A new value is loaded from HDATAM2[6] during reconfiguration.

CFGUSEPLLClock and reset controller

Uses the on-chip PLL to drive the processor and AMBA subsystem (active HIGH).

The reset value is 1. A new value is loaded from HDATAM2[10] during reconfiguration.

CFGPLLBYPASSClock and reset controller

Forces the PLL output to be bypassed (active HIGH).

The reset value is 0. A new value is loaded from HDATAM2[11] during reconfiguration.

CFGPLLSHORTFBClock and reset controller

Removes the clock tree delay from the PLL feedback (active HIGH).

The reset value is 0. A new value is loaded from HDATAM2[12] during reconfiguration.

CFGHCLKDIVSEL[1:0]Clock and reset controller

Sets the CLK to HCLK divide ratio. The divide value is set as follows:

b00 = 1b01 = 2b10 = 3b11 = 4.

The reset value is b01. A new value is loaded from HDATAM2[14:13] during reconfiguration.

CFGHCLKEXTDIVSEL[2:0]Clock and reset controller

Sets the HCLK to HCLKEXT divide ratio. The divide value is set as follows:

b000 = 1b001 = 2b010 = 3b011 = 4
b100 = 5
b101 = 6
b110 = 7
b111 = 8.

The reset value is b001. A new value is loaded from HDATAM2[17:15] during reconfiguration.

CFGMBXCLKDIVSEL[1:0]MBX Graphics Accelerator, CLKRATIO[1:0]

Sets the HCLK to MBXCLK divide ratio. The divide value is set as follows:

b00 = 1b01 = 2b10 = 3b11 = 4.

The reset value is b01. A new value is loaded from HDATAM2[19:18] during reconfiguration.

CFGSMCCLKDIVSEL[1:0]SSMC, SMMEMCLKRATIO[1:0]

Sets the HCLK to SMCLK divide ratio for SSMC. The divide value is set as follows:

b00 = 1b01 = 2b10 = 3b11 = 4.

The reset value is b01. A new value is loaded from HDATAM2[21:20] during reconfiguration.

CFGAHBM1ASYNCOff-chip AHB bridge 1 and clock and reset controller

Force off-chip bridge 1 to asynchronous mode (active HIGH).

The reset value is 0. A new value is loaded from HDATAM2[22] during reconfiguration.

CFGAHBM2ASYNCOff-chip AHB bridge 2 and clock and reset controller

Force off-chip bridge 2 to asynchronous mode (active HIGH).

The reset value is 0. A new value is loaded from HDATAM2[23] during reconfiguration.

CFGAHBSASYNCOn-chip AHB bridge and clock and reset controller

Force the on-chip bridge to asynchronous mode (active HIGH).

The reset value is 0. A new value is loaded from HDATAM2[24] during reconfiguration.

CFGAHBPASSTAll AHB bridges

Switch the off-chip and on-chip bridges to pass-through mode (active HIGH).

The reset value is 0. A new value is loaded from HDATAM2[25] during reconfiguration.

CFGINCROVERRIDEM1Off-chip AHB bridge 1

Override burst transfer with INCR mode (active HIGH).

The reset value is 0. A new value is loaded from HDATAM2[26] during reconfiguration.

CFGINCROVERRIDEM2Off-chip AHB bridge 2

Override burst transfer with INCR mode (active HIGH).

The reset value is 0. A new value is loaded from HDATAM2[27] during reconfiguration.

CFGINCROVERRIDESOn-chip AHB bridge

Override burst transfer with INCR mode (active HIGH).

The reset value is 0. A new value is loaded from HDATAM2[28] during reconfiguration.

Figure 2.6. Power-on configuration block diagram

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